mSGDMA DDR3 errors in data saved after X bytes

I have Qsys system consisting of NIOS (+ associated peripherals), mSGDMA dispatcher, mSGDMA write master and custom block with avalon stream output.

Dispatcher settings:

• Streaming to Memory Mapped

• Memory mapped response port

• Fifo depth: 1024

Write master settings

• Data width: 32

• Fifo depth: 4096

• Length Width: 26

• Burst disabled

Custom block properties

• 32 bit output of 0 - 4095 counter

• 8 bit symbol

I am setting up my descriptors using the following code:

 
  
      for(i = 0; i < NUMBER_OF_BUFFERS; i++){         
             // Hold until there is space to add another descriptor.        
             while ((RD_CSR_STATUS(STREAM_DISPATCHER_CSR_BASE) & CSR_DESCRIPTOR_BUFFER_FULL_MASK) != 0) {}        
            
             // Set up descriptor control bits on last buffer to interupt when finished.        
             controlBits = (i == (NUMBER_OF_BUFFERS-1))? DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK : DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK ;        
             construct_standard_st_to_mm_descriptor(pStdDescriptor,(alt_u32 *)writeAddress, BUFFER_SIZE, controlBits);        
             write_standard_descriptor (STREAM_DISPATCHER_CSR_BASE, STREAM_DISPATCHER_DESCRIPTOR_SLAVE_BASE, pStdDescriptor);     
     }

BUFFER_SIZE = 16kb

NUMBER_OF_BUFFERS = 4

My intention is to move 16kb blocks of data into 4 separate buffers in DDR3 memory. At the end of the 4th buffer, I interrupt and reset the descriptor chain. The delay between the end of the chain and the start of the new one is a problem for me as it means losing data. But that is not my current concern. The problem that I am having at the minute is that there are a lot of errors in the data saved to the DDR3. The data looks perfect up until around the same point every time (~5100 bytes/ 1275 words). This is well inside the first descriptor transfer.

The second descriptor in the chain again starts error free for similar length before errors become common. This 2nd descriptor also seems to have a delay in starting transfer after the end of the first descriptor as instead of saving 0 (which the counter rolls over to) it saves 0x693 which is undesirable for my application.

On the 2nd descriptor chain (after restarting in the interrupt service routine), the errors are similar though some occur earlier.

I've attached an image of the diff between the memory contents and what they should be. You can see how the number of errors gets progressively worse.

https://www.alteraforum.com/forum/attachment.php?attachmentid=8573

Has anyone any idea why I am getting these errors? I'm assuming it's something to do with the length of the FIFOs? At the moment I am just setting valid <= '1' on the stream and I am not doing anything with the ready signal (Though signal tapping shows it always to be high).

Any help or ideas appreciated