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Altera_Forum
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12 years ago

mSGDMA DDR3 errors in data saved after X bytes

I have Qsys system consisting of NIOS (+ associated peripherals), mSGDMA dispatcher, mSGDMA write master and custom block with avalon stream output. Dispatcher settings: Streaming to Mem...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks for another response!

My experience with DMA programming is fairly basic so forgive me if I am slow to understand.

The only write to the mSGDMA controller I perform is the write_standard_descriptor call. Following this method through to WR_DESCRIPTOR_WRITE_ADDRESS etc I can see it uses IOWR_32DIRECT to write to the mSGDMA so it's bypassing the cache. I think this applies to any reads by the mSGDMA controller too.

As for invalidating the cache before the DMA starts I flush the cache (alt_dcache_flush_all) before calling start_dispatcher(STREAM_DISPATCHER_CSR_BASE) so I think this accomplishes this.

To investigate whether it's a cache problem further I did switch over to a NIOS II/e so that I dont have a cache and my problem remains the same. Does that confirm the problem is not with the cache as I hope?