Forum Discussion
Altera_Forum
Honored Contributor
12 years agoJust to add some more information to aid any opinions, As long as the descriptor chain is set up to transfer 4096 bytes or less, then no matter how many times I repeat that chain I get correct data.
So I keep coming back to the FIFO depth in the write master. Any opinions on whether this could be my issue? Thanks edit: I've just realised that the offending addresses of DDR3 memory cannot be changed accurately from Eclipse memory debug window either. So it seems my problem may be more with the DDR3 than the mSGDMA. When I write to the same DDR3 addresses from a loop in the NIOS I get almost the exact same pattern of incorrect data. The screencap attached shows the difference between what should just be FFFFFFFF written to a block of memory compared to what is actually found in the DDR3. https://www.alteraforum.com/forum/attachment.php?attachmentid=8582