mSGDMA DDR3 errors in data saved after X bytes

The cpu write to the dma controller registers need to bypass the data cache.

You need to make sure that any data you want the dma controller to read has been flushed from the data cache (to ensure the dma reads the correct data).

You need to invalidate the data cache for the dma target buffer before the dma starts (to ensure the cpu doesn't write back dirty cache lines).