Is it possible to run NIOSV through SDRAM ?

Hello,

Q :May I know does RiscFree IDE report any Run Configuration failure? By saying execute the code, you mean using RiscFree IDE to download ELF into SDRAM right?

A: Yes execute the code means using RiscFree IDE to download ELF into SDRAM, you got it right. And also the RiscFree IDE does not report any Run Configuration failure. There is no problem in downloading the ELF, it works fine up to this point. But my code does get executed as I expect a "Hello World" print as soon as the ELF is loaded, but no success.

Also I tried today to run the ELF in Debug mode, to verify where the NIOSV is getting stuck. On running through Debug Mode, it prompted me to Error : Operation failed : "Command Aborted". Below are the snapshots of error and warnings of Debugger console.

It seems that ELF is loaded successfully into SDRAM, but when trying to read the code from a particular address, it is getting stucked due to unknown reasons.

Any help regarding this could be appreciated. Thanks !!

Also the Debugger Console shows the warning : "Cannot access memory at address 0x2cc" - To which I want to make sure that is NIOSV processor capable to run through the external SDRAM ? If yes, It would be great if I can get a reference design to run NIOSV Code through external SDRAM.

Thanks in advance !!

Best Regards,

Himanshu

Hello,

I have verified that the Debug Module reset for NIOSV is connected to the external SDRAM. Please have a look at the below image for my QSYS configuration.

NIOSV configurations:-

With the above configuration, The NIOSV Code is able to get downloaded into SDRAM without RUN configuration failure in normal mode. But, still it gives me the same pop up error while running the ELF in Debug Mode. Error : Operation failed : "Command Aborted".

Debugger Console warning : "Cannot access memory at address 0x984"

Can you please elaborate in detail for the root cause of such issue ? I am again asking just to confirm that can we run NIOSV through external SDRAM ? If yes, then we can debug further with the hardware design perspective.

Thankyou for the co-operation. Looking forward for your response!!

Regards,

Himanshu.

Hi,

Attached below is a screenshot of the qsys connection between "dbg_reset_out" to "ndm_reset_in" for your reference. You may connect it as of below to the NIOS V ndm_reset_in , external sdram and jtag's reset.

Thank you and looking forward to your feedback after trying the debugging steps.

Regards,

Kelly

Hello,

I have tried to make connection between "dbg_reset_out" to "ndm_reset_in" and also connected it to external sdram and jtag's reset.

With this configuration I again recompiled the design as well as build the software project. But still facing the same issue as I mentioned before. So this did not work out for me. I have attached the snap shot of QSYS system below for your reference.

Also I tried to download the ELF through "niosv-download command" but is doesn't make any differences as well. Lowering the JTAG Frequency to 6MHz also does not work out. So I am stuck at this point to debug further.

I tried to normally do write/read operations in the SDRAM. On-Chip-Ram was used as program memory for this. While doing so, it has been noted that I am able to do 16 bits of write/read transfers successfully. But not able to perform 32-bits of data transfers. May be this can be a issue while reading the ELF stored in the external SDRAM. I will look into this further from my end. But please share your suggestions as well.

Can you please share the PLL configurations for External SDRAM Part No : W9816G6IH ( WinBond ) which has been used on the Cyclone IV E FPGA. What is the minimum clock frequency that needs to be given to SDRAM and also at what phase shift ?

Besides that you can also suggest any fitter assignments which are required for external SDRAM in the QSF file.

Looking forward to hear from you !!!

Regards,

Himanshu

Hello,

I would like to tell inform you that I am not using the OpenOCD Debugging option from the RiscFree IDE. Instead I am using "Ashling RISCV (auto-detect) hardware debugging option.

Hi Kelly,

I've also been trying to run a Nios V system on a DE10-Lite board (MAX 10 device). I implemented a very simple Hello World project. Everything goes fine when I use the default on-board clock (50 MHz) and the on-chip memory. But, like Himanshu, the system fails to run when using the SDRAM instead of the on-chip memory. The SDRAM requires a PLL for both overclocking (100 MHz) and appropriate timing, so I simply used the same PLL and configuration as for a Nios II project.

Then, I noticed that the Nios V system does not work with a 100 MHz PLL (using on-chip ram only). When configuring the PLL at 50 MHz, everything works fine again (still with on-chip ram only).

Did I miss something while configuring my system, or is there an issue with overclocking the Nios V?

Below is a screenshot of my Platform Designer system for the Nios V configuration.

Best regards

Vincent

Sure. Would be waiting for your response

Hi,

I know that SDRAM Controller IP is no more supported in the latest Quartus Versions. But I would like to inform you that I have the .TCL file that will generate source of SDRAM Controller IP and it's path is added in the user_components.ipx file. The .TCL will show the SDRAM Controller IP in the QSYS system. It is an older version of SDRAM Controller IP which I am using.

The SDRAM Controller IP, which I am using is from older Quartus 18.x version. To use in the latest Quartus Versions, we need to add the .TCL file in the IP_IPX_PATH variable which have file user_components.ipx.

You can ask INTEL to provide the TCL of the SDRAM Controller IP,

Regards,

Himanshu