Occasional Contributor
Frequent ContributorHi Himanshu,
Could you send me a screenshot of the OpenOCD error logs for me to investigate further.
Thank you.
Kelly
New ContributorHi Kelly,
I've also been trying to run a Nios V system on a DE10-Lite board (MAX 10 device). I implemented a very simple Hello World project. Everything goes fine when I use the default on-board clock (50 MHz) and the on-chip memory. But, like Himanshu, the system fails to run when using the SDRAM instead of the on-chip memory. The SDRAM requires a PLL for both overclocking (100 MHz) and appropriate timing, so I simply used the same PLL and configuration as for a Nios II project.
Then, I noticed that the Nios V system does not work with a 100 MHz PLL (using on-chip ram only). When configuring the PLL at 50 MHz, everything works fine again (still with on-chip ram only).
Did I miss something while configuring my system, or is there an issue with overclocking the Nios V?
Below is a screenshot of my Platform Designer system for the Nios V configuration.
Best regards
Vincent
Occasional ContributorHi Vincent,
I would like to advice you to add a Avalon MM Pipeline Bridge IP between SDRAM Controller and NIOSV Processor. By doing this you would be able to run software from SDRAM. Below is the configuration of Avalon MM Pipeline Bridge for your reference.
The MASTER Interface of Avalon MM Pipeline Bridge IP must be connected to SDRAM Controller IP and the SLAVE Interface of Avalon MM Pipeline Bridge IP must be connected to NIOSV Processor.
I hope by doing the above change, you will be able to run your software through SDRAM.
Best Regards,
Himanshu
New ContributorHi Himanshu,
Thanks for your help. I will try it as soon as I receive a reply from Intel regarding the use of a PLL to overclock the NIOS V. The SDRAM on the DE10-Lite board requires at least a 100 MHz clock to run properly, so the whole system needs to be overclocked. NIOS II works perfectly well at 100 MHz, but it seems there is an issue with overclocking the NIOS V, or maybe (probably) I'm missing something.
Thanks again
Best regards
Vincent
New ContributorHi Himanshu,
This message to inform you, and everyone in the Intel/Terasic community who might be interested, that I managed to implement a NIOS V using the SDRAM on a DE10-Lite board. A few things need to be carefully considered though if you want the system to work.
First, it seems the NIOS V is unable to run at 100 MHz on the DE10-Lite board (while the NIOS II has no problems at 100 MHz). The timing analysis revealed that the maximum frequency is slightly above 95 MHz (maybe Intel people could confirm or otherwise indicate how to improve the NIOS V top frequency on that board). So, I lowered the speed down to 90 MHz (using the altpll IP). By lowering the frequency, I feared the SDRAM module wouldn't work properly since the manufacturer recommends higher frequencies, but it seems to be robust against frequency changes.
Second, you need to select at least the Performance (High-effort - increases runtime) optimization mode in the Compiler Settings. In Balanced mode, the system seems to fail reaching the required timing performance.
Normally, by doing this, you're in business...!
I would also like to add that I experienced some strange behaviours on Ashling RiscFree IDE. First, sometimes the program fails to updated when I want to run a new version. Say for instance, I first run a simple 'Hello World' and then I want to add new instructions, the simple 'Hello World' keeps on running (even when terminating the program properly from the console). I have to restart the whole download process over, and sometimes even need to reset the system before the new app version is taken into account. Any idea where this issue might come from?
Best regards
Vincent
