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himanshuvaria's avatar
himanshuvaria
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Is it possible to run NIOSV through SDRAM ?

Hello, I am developing a project where NIOS II needs to replaced with NIOSV processor. When my design was having NIOS II as CPU, I was running the software code through External SDRAM on the Cyclon...
Embedded Applications Layer
Nios Cpu
KellyJialin_Goh's avatar
KellyJialin_Goh
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,

Thank you for the information provided. Running NIOS V through external SDRAM should be possible.


Could you try to make the connection between "dbg_reset_out" to "ndm_reset_in" ? I will attach a screenshot on this qsys connection.


Also, could you try to use niosv-download command to try downloading elf to run the application and lowering the JTAG frequency to 6Mhz to check whether is it a RiscFree issue.


Thank you,


Regards,

Kelly


  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,

    Attached below is a screenshot of the qsys connection between "dbg_reset_out" to "ndm_reset_in" for your reference. You may connect it as of below to the NIOS V ndm_reset_in , external sdram and jtag's reset.

    Thank you and looking forward to your feedback after trying the debugging steps.

    Regards,

    Kelly

  • himanshuvaria's avatar
    himanshuvaria
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello,

    I have tried to make connection between "dbg_reset_out" to "ndm_reset_in" and also connected it to external sdram and jtag's reset.

    With this configuration I again recompiled the design as well as build the software project. But still facing the same issue as I mentioned before. So this did not work out for me. I have attached the snap shot of QSYS system below for your reference.

    Also I tried to download the ELF through "niosv-download command" but is doesn't make any differences as well. Lowering the JTAG Frequency to 6MHz also does not work out. So I am stuck at this point to debug further.

    I tried to normally do write/read operations in the SDRAM. On-Chip-Ram was used as program memory for this. While doing so, it has been noted that I am able to do 16 bits of write/read transfers successfully. But not able to perform 32-bits of data transfers. May be this can be a issue while reading the ELF stored in the external SDRAM. I will look into this further from my end. But please share your suggestions as well.

    Can you please share the PLL configurations for External SDRAM Part No : W9816G6IH ( WinBond ) which has been used on the Cyclone IV E FPGA. What is the minimum clock frequency that needs to be given to SDRAM and also at what phase shift ?

    Besides that you can also suggest any fitter assignments which are required for external SDRAM in the QSF file.

    Looking forward to hear from you !!!

    Regards,

    Himanshu

    • himanshuvaria's avatar
      himanshuvaria
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi,

      Below is the snap shot of my SDRAM Controller IP configurations. Please have a look and verify if the configurations are correct for Cyclone IV E (EP4CE40F23C8).

      Regards,

      Himanshu

      • Vincent_F's avatar
        Vincent_F
        Icon for New Contributor rankNew Contributor
        1 year ago

        Hi Himanshu,

        Like you, I've been looking for a way to use SDRAM together with the NIOS V. I came across your above post where you shared a Platform Designer screenshot of your system featuring a NIOS V and the SDRAM Controller Intel FPGA IP. I was wondering how you managed to have access to this controller, since it seems this IP is no longer supported on Quartus 23.1. Which version of Quartus do you use?

        Thanks in advance for your help.

        Best regards

        Vincent