Occasional Contributor
Frequent ContributorHi Himanshu,
Could you send me a screenshot of the OpenOCD error logs for me to investigate further.
Thank you.
Kelly
Occasional ContributorHello,
I would like to tell inform you that I am not using the OpenOCD Debugging option from the RiscFree IDE. Instead I am using "Ashling RISCV (auto-detect) hardware debugging option.
Occasional ContributorAlso I would like to mention some related information regarding the issues. The SDRAM consists 16 bit data bus while the data bus of NIOSV bus is 32 bits. Although the tool should be able to manage both the interfaces on its own, but to verify I created another simple design where I used On-Chip-Ram as program memory with 16 bits data width. Now my NIOSV code should work with 16 bit On-Chip-Ram but somehow I faced the same issue which I was facing while using external SDRAM as program memory. The NIOSV ELF gets loaded successfully without Run Failure but does not get executed. While running through Debug("Ashling RISCV (auto-detect) hardware debugging option), I faced the similar issues as I was facing for external SDRAM. The Debugger console shows the warning, "Cannot Access memory at address 0x2b4".
I am attaching the design here for your reference. Please have a look and give your feedback !!
Can NIOSV run with 16 bit On-Chip-Ram. If yes, then why it is resulting in such kind of errors. Only if I change the data width of On-Chip-Ram to 32 bits, everything works fine. But with 16 bit, it is having issues while accessing the code. I think similar issues were there with SDRAM as the data bus of SDRAM is 16 bits.
Please find a solution regarding this. Thanks !!
Regards,
Himanshu
New ContributorHi Kelly,
I've also been trying to run a Nios V system on a DE10-Lite board (MAX 10 device). I implemented a very simple Hello World project. Everything goes fine when I use the default on-board clock (50 MHz) and the on-chip memory. But, like Himanshu, the system fails to run when using the SDRAM instead of the on-chip memory. The SDRAM requires a PLL for both overclocking (100 MHz) and appropriate timing, so I simply used the same PLL and configuration as for a Nios II project.
Then, I noticed that the Nios V system does not work with a 100 MHz PLL (using on-chip ram only). When configuring the PLL at 50 MHz, everything works fine again (still with on-chip ram only).
Did I miss something while configuring my system, or is there an issue with overclocking the Nios V?
Below is a screenshot of my Platform Designer system for the Nios V configuration.
Best regards
Vincent
Occasional ContributorHi Vincent,
I would like to advice you to add a Avalon MM Pipeline Bridge IP between SDRAM Controller and NIOSV Processor. By doing this you would be able to run software from SDRAM. Below is the configuration of Avalon MM Pipeline Bridge for your reference.
The MASTER Interface of Avalon MM Pipeline Bridge IP must be connected to SDRAM Controller IP and the SLAVE Interface of Avalon MM Pipeline Bridge IP must be connected to NIOSV Processor.
I hope by doing the above change, you will be able to run your software through SDRAM.
Best Regards,
Himanshu
New ContributorHi Himanshu,
Thanks for your help. I will try it as soon as I receive a reply from Intel regarding the use of a PLL to overclock the NIOS V. The SDRAM on the DE10-Lite board requires at least a 100 MHz clock to run properly, so the whole system needs to be overclocked. NIOS II works perfectly well at 100 MHz, but it seems there is an issue with overclocking the NIOS V, or maybe (probably) I'm missing something.
Thanks again
Best regards
Vincent
