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Altera_Forum's avatar
Altera_Forum
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20 years ago

How to reset a single component

Lets consider following scenario:

I have a PCI card equipped with a cyclone2 device. It is programmed with an SOPC builder system which contains a NIOS2 core,

a PCI bridge and several other custom IP blocks with busmaster functionality. The data and code memory of the NIOS are accessible

from the windows/linux PC via the PCI bridge.

Now i want to update the NIOS program memory during run time (not of the NIOS system, but of the other blocks...).

I think the best way to do this, is to assert the NIOS reset, upload the new software and deassert reset again.

But how can i access the reset of the NIOS core via the PCI bridge, without generating a system wide reset?

Any ideas someone?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Stonie,

    I don't know if I understand you right: Is your problem how to generate a reset signal via PCI, or to isolate NIOS-reset from other SOPC builder devices' reset ?

    My design is similar to yours and I've choosed another way to update the current firmware: A special command (via PCI) forces the CPU to jump into an endless wait-loop, which is placed at intenal ROM. Every variable used, is also located in a small internal RAM. So the complete system memory is now unused and can be overwritten via PCI, until a reset pulse restarts NIOS or a special command forces NIOS to fetch its new reset vector and restarts.

    Mike
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    My problem is more or less both of them:

    I want to set the NIOS in reset state via PCI bridge without affecting all other devices - then do the update - and finally release the NIOS reset again.

    Unfortunately, your solution is not applicable because i don't have external RAM, and internal RAM is very limited....
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi stonie,

    I had a similar problem ... I wanted to keep the Nios-II core in reset, but still write

    to sdram via a PCI bridge. But a reset of the system module also reset the SDRAM

    controller 8-P

    As it turns out, I ended up moving the sdram controller and the PCI bridge (and

    some PCI accessible control registers) out of the SOPC system module that contained

    the Nios-II. Basically, I ended up with two system modules: 1-with the Nios-II core

    and various I/O, and 2-with the SDRAM controller. The PCI bridge (and control regs)

    were external to both. The system module with the SDRAM controller had two slave

    interfaces (one for the Nios-II module and the other for the PCI bridge).

    This structure was a pain-in-the-@$$, but it let me keep separate resets without

    having to hack things up. An independent "CPU reset" signal from the system module

    would certainly make like easier (hint hint).

    Regards,

    --Scott
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    MY first thought was to write a container for the NIOS core with an additional slave port which contains a single bit register. The output of this register could be ORed to the SOPC builders reset line - but i don't know if this will compile with future NIOS versions???