Forum Discussion
Altera_Forum
Honored Contributor
20 years agoStonie,
I don't know if I understand you right: Is your problem how to generate a reset signal via PCI, or to isolate NIOS-reset from other SOPC builder devices' reset ? My design is similar to yours and I've choosed another way to update the current firmware: A special command (via PCI) forces the CPU to jump into an endless wait-loop, which is placed at intenal ROM. Every variable used, is also located in a small internal RAM. So the complete system memory is now unused and can be overwritten via PCI, until a reset pulse restarts NIOS or a special command forces NIOS to fetch its new reset vector and restarts. Mike