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Altera_Forum
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14 years ago

HELP!!- NiosII Error message and customized SRAM

Hi,

I am a beginner on NiosII. I was recently attracted very much by new features provide by series of new development tools. I am currently facing two problems. I have spent more than one week on trying to solve the two problems, but no progress. That may be because I still didn’t understand the whole system deeply. I hope the experts/professionals here could help me out. Thanks in advance.

my developing environment:

- QuartusII 10.1

- Modelsim 6.6C

- NiosII for Eclipse 10.1

- Windows XP Chinese version

- Target hardware: CycloneIII EP3C16F484 + two 16bits SRAM(connected as 32bits system, IS61WV25616) + 40M external clock + Jtag

-

1. first problem – errors come out when run helloworld

The HelloWorld project is estabilished as “NiosII Application and BSP from Template”. It could be built successfully. but when I try to run the program, the following error message come out:

**CPU Master Group not set

**CPU Architecture Type not set

**The SOPC design doesn’t contain a CPU of a supported architecture.

**CPU module not set

But the program can be run correctly with these error messages. I can see “Hello World” in Console window.

I tried another program which is programmed by myself. It is simply to drive on/off the two LEDs on target hardware. It could be built correctly. When run, the same error message comes again. But still it seems could be run correctly. I can see the two LED are driven on/off as designed.

Does anybody know the root cause of the problem? How to fix it?

2. second problem – could not use customized sram correctly.

As indicated as above, I use two 16bits SRAM one 32bits system. I tried two methods to build customized SRAM

#1 connect the two SRAMs onto Avalon tri-state bus and then define signal and interface as following

iCLK clock_sink clk 1 input

ADDR conduit_end export 19 output

DATA conduit_end export 32 bidir

nLB1 conduit_end export 1 output

nLB0 conduit_end export 1 output

nUB1 conduit_end export 1 output

nUB0 conduit_end export 1 output

nCE conduit_end export 1 output

nOE conduit_end export 1 output

nWE conduit_end export 1 output

iADDR Avalon_tristate_slave address 21 output

iDATA avalone_tristate_slave data 32 bidir

inWE avalone_tristate_slave write_n 1 input

inOE avalone_tristate_slave read_n 1 input

inCE avalone_tristate_slave 1 chipselect_n input

inBE avalone_tristate_slave 4 byteenable_n input

the vhdl code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library std;

use std.textio.all;

entity NewComponents is

port (

--Avalon side

signal iADDR: IN STD_LOGIC_VECTOR(20 downto 0);

signal iDATA: INOUT STD_LOGIC_VECTOR(31 downto 0);

signal inBE: IN STD_LOGIC_VECTOR(3 downto 0);

signal inCE: IN STD_LOGIC;

signal inOE: IN STD_LOGIC;

signal inWE: IN STD_LOGIC;

signal iCLK: IN STD_LOGIC;

--Output Port

signal ADDR: OUT STD_LOGIC_VECTOR(18 downto 0);

signal DATA: INOUT STD_LOGIC_VECTOR(31 downto 0);

signal nLB0: OUT STD_LOGIC;

signal nLB1: OUT STD_LOGIC;

signal nUB0: OUT STD_LOGIC;

signal nUB1: OUT STD_LOGIC;

signal nCE: OUT STD_LOGIC;

signal nOE: OUT STD_LOGIC;

signal nWE: OUT STD_LOGIC);

end entity NewComponents;

ARCHITECTURE BEHAVIOUR of NewComponents IS

BEGIN

nLB0 <= inBE(0);

nLB1 <= inBE(1);

nUB0 <= inBE(2);

nUB1 <= inBE(3);

nCE <= inCE;

nWE <= inWE;

nOE <= inOE;

ADDR(0) <= iADDR(2);

ADDR(1) <= iADDR(3);

ADDR(2) <= iADDR(4);

ADDR(3) <= iADDR(5);

ADDR(4) <= iADDR(6);

ADDR(5) <= iADDR(7);

ADDR(6) <= iADDR(8);

ADDR(7) <= iADDR(9);

ADDR(8) <= iADDR(10);

ADDR(9) <= iADDR(11);

ADDR(10) <= iADDR(12);

ADDR(11) <= iADDR(13);

ADDR(12) <= iADDR(14);

ADDR(13) <= iADDR(15);

ADDR(14) <= iADDR(16);

ADDR(15) <= iADDR(17);

ADDR(16) <= iADDR(18);

ADDR(17) <= iADDR(19);

ADDR(18) <= iADDR(20);

process(iCLK)

begin

if(iCLK'event and iCLK = '1')then

if(inCE = '0' and inWE = '0')then

DATA <= iDATA;

elsif(inCE ='0' and inOE ='0')then

iDATA <= DATA;

else

iDATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

DATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

end if;

end if;

end process;

End BEHAVIOUR;

Then build and run “HelloWorld”, below error messages appeared:

**Downloading ELF process failed

I guess this because the SRAM is not run.

Another strange thing I found is that the Avalon interface of iDATA[31..0] appeared in symbol when I checked in quartusII. This has alreadybeen defined as Avalon interface, so I think it should not be on component port.

#2 I connect the two SRAM onto Avalon_slave, not tristate. I defined two data bus, one is for input and another for output. The runing result is the same as# 1.

Could somebody told me where are mistakes?

Sorry for the long email. I could not paste pictures, so I have to describe in words. I am waiting for answers. Thank you all.

Jeffrey

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I don't know about the errors in question 1. For question 2, you don't need to export the address and data busses. When you define add the avalon tristate bridge in SOPC builder, just select what signals you want SOPC builder to export for you and it will do it for you. You should at least select the data and address busses.

    What you could do to test your setup is to run a memory test software from the on-chip memory and use it to test your SSRAM. Using Signaltap probes can also help you understand what is going on.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks Daixiwen for your reply.

    I didn't find where I can select what signals I want SOPC to export if they are not defined as "conduit_end export"

    Yes, I did tried to run SRAM memory test program. But I could not make it working. When run, it always stops with the error "ELF downloading process failed". I will try again. Using Signaltap probes is a good idea. Thanks again.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I haven't used the tristate bus in a while but IIRC those signals to exports are defined when you double click on the tristate bridge, not when you define the interfaces on your custom component.

    For the memory test, chuck that you put everything (code, stack, heap) in the onchip memory and not on the ram you want to check.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks Daixiwen,

    I got what you said about exporting signals. It is in second page of Alalon_MM Tristate Bridge - Shared Signals.

    My understanding for export signals is that they are represent the real/phsical signals which should connect to pins of FPGA.

    As you suggested, I just only define signals for avalon tristate interface, didn't define any exports. After complilation, the signals defined as tristate interface are all appeared in QuartusII symbol as real pins, it is correct?

    I checked on data and address bus as shared signals.

    Then I run memory test program, it says that "data bus test failed at bit 0x1".

    Another thing is that I defined the address width is 19bits(2 chips x 256 x 16bits). After generation, in quartusII side, the address width turn into 21bits, I use A2 to A20 and just leave A0 and A1 to be unconnected, is this correct?

    Thanks Again.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    progress:

    The SRAM can be built correctly when I follow below procedure:

    1. add HDL file into new components

    2. only keep ADDR, DATA, CS, OE, WE, BE and CLK, set them as tristate_slave(except CLK) and then delete all other ports

    3. delete HDL file

    4. in this case, only two ports for the new components: clock_sink and avalon_tristate_slave

    But if I don't use HDL, just add new signals into the new components and assign interface as tristate slave, three parts would be appeared in GUI of the components: clock_sink, avalon_tristate_slave and avalon_tristate_slave1(conduit).

    I don't know why one more port is appeared. I tried, but have no any clue to fix it.

    Does any body know?

    thanks
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    About SRAM, HDL must be required? I couldn't make it working without writing HDL. Can somebody share VHDL code for SRAM for my reference? I think I didn't understand what should be implemented in VHDL code.

    thanks
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    SRAM problem is still not fixed completely. But I have made great progress. I am able to use my customized SRAM at sometimes. It is very interesting that it sometimes works well and sometimes not. I can make sure the operations are exactly the same. The hardware system I built is very simple: NiosII + JTAG + system ID + Avalon Tristate + external SRAM.

    I am suspecting it is caused by software bugs. QuartusII, SOPC builder and NiosII Eclipse crashed several times. I can reproduce some of bugs.

    I am facing another problem. After compilation of QuartusII, "Node Names" in Pin Planner are the names of component ports, not the pins names. The names defined for pins don't appear in "Node Name". Does anyboday know the reason?

    thanks
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    concerning your sram problem : Why you don't use the SOPC-Builder provided SRAM controller ?

    If you want to create your own sram controller you do not need a hdl file, you can use the attached tcl script. Maybe you have to adjust the timings for read and write to your sram timing.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi HJS,

    Thanks for your reply and attachment.

    There are only two types of SOPC provided SRAM controllers which don't fit the SRAM that I use. So I have to create my own SRAM controller.

    Yes, I finally learnt that HDL file is not mandantory for creating own SRAM controller.

    I finally figured out the root cause of my problem. In Quartus II, I defined the pin direction of DATA as output which should be bidir actually. After I used right pin direction definition, the SRAM controller works well.

    I don't know why QuartusII doesn't report error or warning when pin direction of self-defined component is not in line with Quartus definition. I think this should be bug or at least it is something that should improve. During this period of study, I did find some bugs for SOPC, NiosII. They can be repeated. I will summarize all of these and then send to Altera. I hope these problems can be solved soon to make sure the software are stable and not so buggy.

    Regarding to problem of# 1, I suspect it is related to NiosII itself. I will consult to Altera for details. By the way, do you have the same problem? It seems to me that it always happen. It is not related to what components I build.

    Thanks again.