HELP!!- NiosII Error message and customized SRAM

progress:

The SRAM can be built correctly when I follow below procedure:

1. add HDL file into new components

2. only keep ADDR, DATA, CS, OE, WE, BE and CLK, set them as tristate_slave(except CLK) and then delete all other ports

3. delete HDL file

4. in this case, only two ports for the new components: clock_sink and avalon_tristate_slave

But if I don't use HDL, just add new signals into the new components and assign interface as tristate slave, three parts would be appeared in GUI of the components: clock_sink, avalon_tristate_slave and avalon_tristate_slave1(conduit).

I don't know why one more port is appeared. I tried, but have no any clue to fix it.

Does any body know?

thanks