HELP!!- NiosII Error message and customized SRAM

Thanks Daixiwen,

I got what you said about exporting signals. It is in second page of Alalon_MM Tristate Bridge - Shared Signals.

My understanding for export signals is that they are represent the real/phsical signals which should connect to pins of FPGA.

As you suggested, I just only define signals for avalon tristate interface, didn't define any exports. After complilation, the signals defined as tristate interface are all appeared in QuartusII symbol as real pins, it is correct?

I checked on data and address bus as shared signals.

Then I run memory test program, it says that "data bus test failed at bit 0x1".

Another thing is that I defined the address width is 19bits(2 chips x 256 x 16bits). After generation, in quartusII side, the address width turn into 21bits, I use A2 to A20 and just leave A0 and A1 to be unconnected, is this correct?

Thanks Again.