Hi Windows 10 ProVersion 2004OS buid 19041.330 Quartus prime version 20.1 Build 711 standard edition The platform designer generates the following error. Error: s0: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally When the platform designer tries to generate HDL code I have tried to both switch on and off the “Windows Subsystem for Linux” according to https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2018/error--s0--error-during-execution-of---c--intelfpga-xx-x-quartus.html but no luck (seems odd to switch off “Windows Subsystem for Linux” when the bat file Nios II Command Shell.bat is using wsl). I can from a command prompt execute the bat file (“Windows Subsystem for Linux” on) C:\intelFPGA\20.1\nios2eds> C:\intelFPGA\20.1\nios2eds>"Nios II Command Shell.bat" ------------------------------------------------ Altera Nios2 Command Shell Version 20.1, Build 711 ------------------------------------------------ stefan@DESKTOP-MH7IPN4:/mnt/c/intelFPGA/20.1/nios2eds$ exit exit C:\intelFPGA\20.1\nios2eds> But the platform designer can not execute it, any ideas ? Regards Info: p0: "ddr3" instantiated altera_mem_if_ddr3_phy_core "p0" Info: m0: "ddr3" instantiated altera_mem_if_ddr3_afi_mux "m0" Error: s0: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Error: s0: Execution of command "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed Error: s0: /mnt/c/intelfpga/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../system_ddr3_s0_AC_ROM.hex -inst_rom ../system_ddr3_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000110001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100110000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000001000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000010000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0 Error: s0: UniPHY Sequencer Microcode Compiler Error: s0: Copyright (C) 2020 Intel Corporation. All rights reserved. Error: s0: Info: Reading sequencer_mc/ac_rom.s ... Error: s0: Info: Reading sequencer_mc/inst_rom.s ... Is it possible to get the content from the stderr.txt files ?

Now Ubuntu 20.04 & version 2 is OK for Quartus 20.1.1. But, Why must I uninstall & reinstall ubuntu ? I can not understand. Please Tell me the reason.

We are in the process of filling a kdb on this. Description:Due to a problem in the Intel® Quartus® Prime Standard Edition software version 20.1 and earlier, you may see the error above when you generate the system in the platform designer.This error happened if you are using updated Windows 10 version and your design consist of DDR4 memory.workaround:To workaround the problem, you can follow the steps below:1) uninstall Ubuntu* 18.04 (if you have one)2) uninstall wsl 3) re-install wsl4) download latest Ubuntu 18.04 from Microsoft Shop & install it5) execute following on Ubuntu shell : sudo apt-get update sudo apt install wsl sudo apt install dos2unix sudo apt install make sudo apt-get upgrade Alternatively, you can refer to here for updating the WSL 2 software.Please take note that Intel does not provide any warranty or guarantee regarding the use of third party software. Hyperlinks to other internet resources are used by you at your own risk.This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Standard edition software.

Error: s0: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.b

47 Replies

IntelSupport

Contributor

5 years ago

We are in the process of filling a kdb on this.

Description:

Due to a problem in the Intel® Quartus® Prime Standard Edition software version 20.1 and earlier, you may see the error above when you generate the system in the platform designer.

This error happened if you are using updated Windows 10 version and your design consist of DDR4 memory.

workaround:

To workaround the problem, you can follow the steps below:

1) uninstall Ubuntu* 18.04 (if you have one)

2) uninstall wsl

3) re-install wsl

4) download latest Ubuntu 18.04 from Microsoft Shop & install it

5) execute following on Ubuntu shell :

sudo apt-get update

sudo apt install wsl

sudo apt install dos2unix

sudo apt install make

sudo apt-get upgrade

Alternatively, you can refer to here for updating the WSL 2 software.

Please take note that Intel does not provide any warranty or guarantee regarding the use of third party software. Hyperlinks to other internet resources are used by you at your own risk.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Standard edition software.

Dooo
New Contributor
4 years ago
Now Ubuntu 20.04 & version 2 is OK for Quartus 20.1.1.

But, Why must I uninstall & reinstall ubuntu ?

I can not understand.

Please Tell me the reason.

SThor8

Occasional Contributor

5 years ago

That's was pretty much what I have done, I have even upgraded to wsl --set-default-version 2.

However, I have hijacked the

C:\intelFPGA\20.1\nios2eds\Nios II Command Shell.bat

like this

wsl bash -c '%NIOS2_SHELL_SCRIPT% %*' 2>> c:\temp\test.txt

And the content in the test.txt file result in

/mnt/c/intelfpga/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp: line 451: nios2-bsp-update-settings: command not found
nios2-bsp: nios2-bsp-update-settings failed
make: *** [setup] Error 1

Line 451 in nios2-bsp look like this

        nios2-bsp-update-settings$windows_exe --settings "$settings_pname" --bsp-dir $bsp_dir --sopc "$sopc_design_file" --script "$default_tcl"  ${default_tcl_options[@]} ${create_update_options[@]} || {

So if I change the line temporarily into

        /mnt/c/intelfpga/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp-update-settings$windows_exe --settings "$settings_pname" --bsp-dir $bsp_dir --sopc "$sopc_design_file" --script "$default_tcl"  ${default_tcl_options[@]} ${create_update_options[@]} || {

Now the script will "find" nios2-bsp-update-settings and execute it

The problem is that
your are missing paths to your scripts and/or
changing to the installation directory when executing the scripts and/or adding a installation path prefix to your scripts and/or
update the PATH variable so it can find the scripts in /mnt/c/intelfpga/20.1/quartus/../nios2eds/sdk2/bin,
(${_ACDS_ROOT}/nios2eds/sdk2/bin).

The script executing system is currently in directory
/mnt/c/Users/StefanThorlacius/AppData/Local/Temp/alt8456_4792771601944741470.dir/0253_s0_gen/qsys_pre_compile/system_ddr3_s0_software
and can not "find" nios2-bsp-update-settings.exe in /mnt/c/intelfpga/20.1/quartus/../nios2eds/sdk2/bin

Line 451 in nios2-bsp, expanded, look like this

nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE

it will generate the error message in Generate HDL log window

Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred
    while executing
"error "An error occurred""
.............................

nios2-bsp-update-settings is a binary file, so I have difficulties to examine this further

Regards

SThor8

Occasional Contributor

5 years ago

Your suggestions is what I did in first place but the error remain

You should change the line 37 in ${_ACDS_ROOT}/nios2eds/sdk2/bin/nios2-bsp from

if [[ $uname =~ "Microsoft" ]]; then

into

if [[ $uname =~ "Microsoft" || $uname =~ "microsoft" ]]; then

On my machine uname will return

uname = '4.19.104-microsoft-standard'

then the nios2-bsp script will be able to execute line 451

nios2-bsp-update-settings$windows_exe --settings "$settings_pname" --bsp-dir $bsp_dir --so

($windows_exe will be set correctly)

This get ride of the first execution error and the scripts can move forward.

Now the scripts encounter the following error in the "Generate HDL log"

Error: s0: Cannot find sequencer/sequencer.elf

Which seems to be related to

WARNING: The BSP persisted OS version "9.1" is not available. The default latest BSP version will be used instead. 
WARNING: The BSP being loaded used OS version "9.1". The BSP version "20.1" will be used instead. 
Makefile:515: Warning: SOPC File C:/Users/StefanThorlacius/AppData/Local/Temp/alt8456_4792771601944741470.dir/0533_s0_gen/qsys_pre_compile/pre_compile.sopcinfo could not be found.
make[2]: nios2-elf-gcc: Command not found
make[2]: *** [obj/HAL/src/alt_dcache_flush_all.o] Error 127
make[1]: *** [../sequencer_bsp-recurs-make-lib] Error 2
make: *** [elf] Error 2

SThor8

Occasional Contributor

5 years ago

If above suggestion to nios2-bsp is correct then line 28 in ………./20.1/nios2eds nios2_command_shell.sh should be changed from

if [[ $uname =~ "Microsoft" ]]

if [[ $uname =~ "Microsoft" || $uname =~ "microsoft" ]]

as well

KennyT_altera
Super Contributor
5 years ago
Thanks, seems like there is a patch needed before upgrading the WSL.

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2020/fatal--cannot-generate-ip-in-a-windows-evironment-.html

I will get the patch for you in 20.1
- SThor8
  Occasional Contributor
  5 years ago
  Nice, thanks a lot
KennyT_altera
Super Contributor
5 years ago
i had reported this issue to the developer.

Can you do us a favor, install Q19.1 with the patch to see it resolve the issue?
- SThor8
  Occasional Contributor
  5 years ago
  Hi
  
  The original project is made in 20.1 and the downgrading did not work well so I could not actually compile it.
  
  However, after applying the 19.1 patch on Quartus 19.1, I could see that the scripts will still fail due to the constructions
  
  uname=$(uname -r) if [[ $uname =~ "Microsoft" ]]; then
KennyT_altera
Super Contributor
5 years ago
You may use this design

https://rocketboards.org/foswiki/Documentation/GSRD131CompileHardwareDesign

Check whether emif/hps emif exist there and upgrade the design.

Compile the design in Q20.1 and Q19.1 with patch.
- SThor8
  Occasional Contributor
  5 years ago
  Hi
  
  Here is the result, but I guess it does not address the original problem I have.
  
  Do you want to send my email to the developer so I can test any patches quicker?
  
  Rebgards
  
  Quartus 19.1, no patch, project cv_soc_devkit_ghrd
  
  Platform designer, Generate HDL, Pass
  Info: soc_system: Done "soc_system" with 64 modules, 130 files
  Info: qsys-generate succeeded.
  Info: Finished: Create HDL design files for synthesis
  
  Project, compile: Failed
  Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
  Info (144001): Generated suppressed messages file C:/Users/StefanThorlacius/Downloads/cv_soc_devkit_ghrd_19_1/output_files/soc_system.map.smsg
  Error: Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 33 warnings
  Error: Peak virtual memory: 5126 megabytes
  Error: Processing ended: Fri Jul 17 06:33:04 2020
  Error: Elapsed time: 00:03:28
  Error: Total CPU time (on all processors): 00:03:36
  
  Quartus 19.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd
  
  Platform designer, Generate HDL, Pass
  Info: soc_system: Done "soc_system" with 64 modules, 130 files
  Info: qsys-generate succeeded.
  Info: Finished: Create HDL design files for synthesis
  
  Project, compile: Failed
  Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
  Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
  Error: Peak virtual memory: 5181 megabytes
  Error: Processing ended: Fri Jul 17 06:42:22 2020
  Error: Elapsed time: 00:00:14
  Error: Total CPU time (on all processors): 00:00:13
  Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings
  
  Quartus 20.1, no patch, project cv_soc_devkit_ghrd
  
  Platform designer, Generate HDL, Pass
  Info: soc_system: Done "soc_system" with 64 modules, 130 files
  Info: qsys-generate succeeded.
  Info: Finished: Create HDL design files for synthesis
  
  Project, compile: Failed
  Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
  Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
  Critical Warning (169085): No exact pin location assignment(s) for 83 pins of 157 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
  Error (174068): Output buffer atom "soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination
  ....
  ....
  ....
  Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
  Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
  Error: Peak virtual memory: 5182 megabytes
  Error: Processing ended: Fri Jul 17 05:24:03 2020
  Error: Elapsed time: 00:00:13
  Error: Total CPU time (on all processors): 00:00:12
  Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings
  
  Quartus 20.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd
  
  Platform designer, Generate HDL, Pass
  Info: soc_system: Done "soc_system" with 64 modules, 130 files
  Info: qsys-generate succeeded.
  Info: Finished: Create HDL design files for synthesis
  
  Project, compile: Failed
  Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
  Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
  Critical Warning (169085): No exact pin location assignment(s) for 83 pins of 157 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
  Error (174068): Output buffer atom "soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination
  ....
  ....
  ....
  Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
  Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
  Error: Peak virtual memory: 5182 megabytes
  Error: Processing ended: Fri Jul 17 05:24:03 2020
  Error: Elapsed time: 00:00:13
  Error: Total CPU time (on all processors): 00:00:12
  Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings
- SThor8
  Occasional Contributor
  5 years ago
  
  Hi
  
  You can see below the result, my guess is that this project do not address the problem I have in our project.
  
  Would it be an idea to pass my email to the developer so we can have fast test and turn around time?
  
  Regards Stefan
  
  Quartus 19.1, no patch, project cv_soc_devkit_ghrd
  
  Platform designer, Generate HDL, Pass
  Info: Finished: Create HDL design files for synthesis
  
  Project, compile: Failed
  Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_ava.....................
  Info (144001): Generated suppressed messages file C:/Users/StefanThorlacius/Downloads/cv_soc_devkit_ghrd_19_1/output_files/soc_system.map.smsg
  ....
  ....
  Error: Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 33 warnings
  
  Quartus 19.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd
  
  Platform designer, Generate HDL, Pass
  Info: Finished: Create HDL design files for synthesis
  
  Project, compile: Failed
  Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_ava.....................
  Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
  ....
  ....
  Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings
  
  Quartus 20.1, no patch, project cv_soc_devkit_ghrd
  
  Platform designer, Generate HDL, Pass
  Info: Finished: Create HDL design files for synthesis
  
  Project, compile: Failed
  Error (174068): Output buffer atom ....
  Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger
  
  Quartus 20.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd
  
  Platform designer, Generate HDL, Pass
  Info: Finished: Create HDL design files for synthesis
  
  Project, compile: Failed
  Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
  Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings
KennyT_altera
Super Contributor
5 years ago
I see, can you attached your project to us instead?

might be something missing to fix.
- SThor8
  Occasional Contributor
  5 years ago
  Hi
  
  Is there an email address I can send it to, I do not want to post it this thread.
  
  I could not find you on the internal message list.
  
  PS
  
  Note that one of my colleges can compile it, but he is using an older version of Windows 10 and have not WSL 2
  
  DS
  
  Regards Stefan
KennyT_altera
Super Contributor
5 years ago
You may check your email.

Can you compare the windows version? this one happened only on certain windows 10 update.
- SThor8
  Occasional Contributor
  5 years ago
  Hi
  
  My colleague is on vacation and cannot be reached for another 3 weeks.
  
  My version is
  Windows specification
  Edition: Windows Pro
  Version: 2004
  Installed on: 200-07-13
  OS build : 19041.330
  Expereince: Widnows Feature Experience Pack 120.220230.0
  
  Note: beside that
  
  $ uname -r 4.19.104-microsoft-standard
  
  Microsoft in /proc/version is also spelled small
  
  $ cat /proc/version Linux version 4.19.104-microsoft-standard (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP Wed Feb 19 06:37:35 UTC 2020
  
  The test for Microsoft spelled with m uppercase is also used on various places
  - dncmrc
    Occasional Contributor
    5 years ago
    But I am still left with the second issue:
    
    nios2-elf-gcc.exe: error: CreateProcess: No such file or directory
    
    I have seen there is a patch for 19.1 but we are using Version 19.4.0 Build 64 12/04/2019 SC Pro Edition.
    
    Kenny, could you please get me a patch for 19.4?
    
    Thanks!
KennyT_altera
Super Contributor
5 years ago
Hi,

We manage to narrow down the issue,

For now, the workaround below should work, I had tested out from my side.
- downloaded latest Ubuntu 18.04 from Microsoft Shop & installed it
- executed following on Ubuntu shell :-
- executed following on Ubuntu shell :
sudo apt-get update
sudo apt install wsl
sudo apt install dos2unix
sudo apt install make
sudo apt-get upgrade

Before you use this workaround, you need to check uname -r is if return
4.4.0-17763-Microsoft?

If it return something like 4.19.104-microsoft-standard. The workaround above will not work. The "M" need to be capital letter.

This one usually, is because you might have switch to WSL2. We are currently investigating this and I had let developer know to fix it.

It should accept both capital and small letter.

Thanks,
Best regards,
Kenny
KennyT_altera
Super Contributor
5 years ago
WSL2 is yet supported according the developer. Can make sure that you have switch it back to WSL? Thanks
KennyT_altera
Super Contributor
5 years ago
any update?
- FilipMiler
  New Contributor
  5 years ago
  Hi. I have the same issue when generating "LPDDR2 controller with UniPHY" under Windows build 2004.
  
  The error message apparently starts with "Makefile:543: recipe for target 'obj/HAL/src/alt_dcache_flush_all.o' failed"
  
  It doesn't depend on Quartus version (I tried 19.1 Lite with patch 0.02 and 20.1 Lite), but it does depend on the Windows version, with build 1909 it works fine in both Quartus versions.
  
  uname -r returns "4.4.0-19041-Microsoft" in my case, I'm using Ubuntu 18.04 LTS on WSL 1.
KennyT_altera
Super Contributor
5 years ago
Can you post the full error message? Looking into the short message, it does not seems to be relevant to this thread.
- FilipMiler
 New Contributor
 5 years ago
 The generator unfortunately doesn't output the log into file and it can't be copied en-block from the message window.
 
 But the list of error messages starts with
 
 "Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally"
 
 and ends with
 
 "<html>Error: An error occurred while executing "error "An error occurred"" (procedure "_error" line 8) invoked from within "_error "Cannot find $seq_file"" ("if" then script line 2) invoked from within "if {[file exists $seq_file] == 0} { _error "Cannot find $seq_file" }" (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14) invoked from within "alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"" invoked from within "set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]" ("if" then script line 2) invoked from within "if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} { set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..." (procedure "generate_qsys_sequencer_sw" line 943) invoked from within "generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..." invoked from within "set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..." ("if" else script line 2) invoked from within "if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} { set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..." (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238) invoked from within "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}" invoked from within "set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]" (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3) invoked from within "alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "LPDDR2" $tmpdir QUARTUS_SYNTH" invoked from within "foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "LPDDR2" $tmpdir QUARTUS_SYNTH] { set file_name [file tail $gene..." (procedure "generate_synth" line 8) invoked from within "generate_synth SDRAMController_s0""
 
 The first apparently relevant message in the list is
 
 "Error: Makefile:539: recipe for target 'obj/HAL/src/alt_dcache_flush_all.o' failed"
 
 The "LPDDR2 Controller with UniPHY" uses Nios II for I/O calibration, so it's basicaly the same case as in the first post.

Forum Discussion

Error: s0: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.b

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