Error: s0: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.b

Now Ubuntu 20.04 & version 2 is OK for Quartus 20.1.1.

But, Why must I uninstall & reinstall ubuntu ?

I can not understand.

Please Tell me the reason.

That's was pretty much what I have done, I have even upgraded to wsl --set-default-version 2.

However, I have hijacked the

C:\intelFPGA\20.1\nios2eds\Nios II Command Shell.bat

like this

wsl bash -c '%NIOS2_SHELL_SCRIPT% %*' 2>> c:\temp\test.txt

And the content in the test.txt file result in

/mnt/c/intelfpga/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp: line 451: nios2-bsp-update-settings: command not found
nios2-bsp: nios2-bsp-update-settings failed
make: *** [setup] Error 1

Line 451 in nios2-bsp look like this

        nios2-bsp-update-settings$windows_exe --settings "$settings_pname" --bsp-dir $bsp_dir --sopc "$sopc_design_file" --script "$default_tcl"  ${default_tcl_options[@]} ${create_update_options[@]} || {

So if I change the line temporarily into

        /mnt/c/intelfpga/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp-update-settings$windows_exe --settings "$settings_pname" --bsp-dir $bsp_dir --sopc "$sopc_design_file" --script "$default_tcl"  ${default_tcl_options[@]} ${create_update_options[@]} || {

Now the script will "find" nios2-bsp-update-settings and execute it

The problem is that
your are missing paths to your scripts and/or
changing to the installation directory when executing the scripts and/or adding a installation path prefix to your scripts and/or
update the PATH variable so it can find the scripts in /mnt/c/intelfpga/20.1/quartus/../nios2eds/sdk2/bin,
(${_ACDS_ROOT}/nios2eds/sdk2/bin).

The script executing system is currently in directory
/mnt/c/Users/StefanThorlacius/AppData/Local/Temp/alt8456_4792771601944741470.dir/0253_s0_gen/qsys_pre_compile/system_ddr3_s0_software
and can not "find" nios2-bsp-update-settings.exe in /mnt/c/intelfpga/20.1/quartus/../nios2eds/sdk2/bin

Line 451 in nios2-bsp, expanded, look like this

nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE

it will generate the error message in Generate HDL log window

Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred
    while executing
"error "An error occurred""
.............................

nios2-bsp-update-settings is a binary file, so I have difficulties to examine this further

Regards

Hi

Your suggestions is what I did in first place but the error remain

You should change the line 37 in ${_ACDS_ROOT}/nios2eds/sdk2/bin/nios2-bsp from

if [[ $uname =~ "Microsoft" ]]; then

into

if [[ $uname =~ "Microsoft" || $uname =~ "microsoft" ]]; then

On my machine uname will return

uname = '4.19.104-microsoft-standard'

then the nios2-bsp script will be able to execute line 451

nios2-bsp-update-settings$windows_exe --settings "$settings_pname" --bsp-dir $bsp_dir --so

($windows_exe will be set correctly)

This get ride of the first execution error and the scripts can move forward.

Now the scripts encounter the following error in the "Generate HDL log"

Error: s0: Cannot find sequencer/sequencer.elf

Which seems to be related to

WARNING: The BSP persisted OS version "9.1" is not available. The default latest BSP version will be used instead. 
WARNING: The BSP being loaded used OS version "9.1". The BSP version "20.1" will be used instead. 
Makefile:515: Warning: SOPC File C:/Users/StefanThorlacius/AppData/Local/Temp/alt8456_4792771601944741470.dir/0533_s0_gen/qsys_pre_compile/pre_compile.sopcinfo could not be found.
make[2]: nios2-elf-gcc: Command not found
make[2]: *** [obj/HAL/src/alt_dcache_flush_all.o] Error 127
make[1]: *** [../sequencer_bsp-recurs-make-lib] Error 2
make: *** [elf] Error 2

Nice, thanks a lot

Hi

The original project is made in 20.1 and the downgrading did not work well so I could not actually compile it.

However, after applying the 19.1 patch on Quartus 19.1, I could see that the scripts will still fail due to the constructions

uname=$(uname -r)
if [[ $uname =~ "Microsoft" ]]; then

Hi

Here is the result, but I guess it does not address the original problem I have.

Do you want to send my email to the developer so I can test any patches quicker?

Rebgards

Quartus 19.1, no patch, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: soc_system: Done "soc_system" with 64 modules, 130 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Info (144001): Generated suppressed messages file C:/Users/StefanThorlacius/Downloads/cv_soc_devkit_ghrd_19_1/output_files/soc_system.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 33 warnings
Error: Peak virtual memory: 5126 megabytes
Error: Processing ended: Fri Jul 17 06:33:04 2020
Error: Elapsed time: 00:03:28
Error: Total CPU time (on all processors): 00:03:36

Quartus 19.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: soc_system: Done "soc_system" with 64 modules, 130 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
Error: Peak virtual memory: 5181 megabytes
Error: Processing ended: Fri Jul 17 06:42:22 2020
Error: Elapsed time: 00:00:14
Error: Total CPU time (on all processors): 00:00:13
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings

Quartus 20.1, no patch, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: soc_system: Done "soc_system" with 64 modules, 130 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (169085): No exact pin location assignment(s) for 83 pins of 157 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Error (174068): Output buffer atom "soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination
....
....
....
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
Error: Peak virtual memory: 5182 megabytes
Error: Processing ended: Fri Jul 17 05:24:03 2020
Error: Elapsed time: 00:00:13
Error: Total CPU time (on all processors): 00:00:12
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings

Quartus 20.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: soc_system: Done "soc_system" with 64 modules, 130 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (169085): No exact pin location assignment(s) for 83 pins of 157 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Error (174068): Output buffer atom "soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination
....
....
....
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
Error: Peak virtual memory: 5182 megabytes
Error: Processing ended: Fri Jul 17 05:24:03 2020
Error: Elapsed time: 00:00:13
Error: Total CPU time (on all processors): 00:00:12
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings

Hi

You can see below the result, my guess is that this project do not address the problem I have in our project.

Would it be an idea to pass my email to the developer so we can have fast test and turn around time?

Regards Stefan

Quartus 19.1, no patch, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_ava.....................
Info (144001): Generated suppressed messages file C:/Users/StefanThorlacius/Downloads/cv_soc_devkit_ghrd_19_1/output_files/soc_system.map.smsg
....
....
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 33 warnings

Quartus 19.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_ava.....................
Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
....
....
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings

Quartus 20.1, no patch, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (174068): Output buffer atom ....
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger

Quartus 20.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings

Hi

Is there an email address I can send it to, I do not want to post it this thread.

I could not find you on the internal message list.

PS

Note that one of my colleges can compile it, but he is using an older version of Windows 10 and have not WSL 2

DS

Regards Stefan

Hi

My colleague is on vacation and cannot be reached for another 3 weeks.

My version is
Windows specification
Edition: Windows Pro
Version: 2004
Installed on: 200-07-13
OS build : 19041.330
Expereince: Widnows Feature Experience Pack 120.220230.0

Note: beside that

$ uname -r
4.19.104-microsoft-standard

Microsoft in /proc/version is also spelled small

$ cat /proc/version
Linux version 4.19.104-microsoft-standard (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP Wed Feb 19 06:37:35 UTC 2020

The test for Microsoft spelled with m uppercase is also used on various places

Hi. I have the same issue when generating "LPDDR2 controller with UniPHY" under Windows build 2004.

The error message apparently starts with "Makefile:543: recipe for target 'obj/HAL/src/alt_dcache_flush_all.o' failed"

It doesn't depend on Quartus version (I tried 19.1 Lite with patch 0.02 and 20.1 Lite), but it does depend on the Windows version, with build 1909 it works fine in both Quartus versions.

uname -r returns "4.4.0-19041-Microsoft" in my case, I'm using Ubuntu 18.04 LTS on WSL 1.

The generator unfortunately doesn't output the log into file and it can't be copied en-block from the message window.

But the list of error messages starts with

"Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally"

and ends with

"<html>Error: An error occurred<br> while executing<br>"error "An error occurred""<br> (procedure "_error" line 8)<br> invoked from within<br>"_error "Cannot find $seq_file""<br> ("if" then script line 2)<br> invoked from within<br>"if {[file exists $seq_file] == 0} {<br> _error "Cannot find $seq_file"<br> }"<br> (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br> invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br> invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br> ("if" then script line 2)<br> invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br> set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br> (procedure "generate_qsys_sequencer_sw" line 943)<br> invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."<br> invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."<br> ("if" else script line 2)<br> invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br> set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br> invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "LPDDR2" $tmpdir QUARTUS_SYNTH"<br> invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "LPDDR2" $tmpdir QUARTUS_SYNTH] {<br> set file_name [file tail $gene..."<br> (procedure "generate_synth" line 8)<br> invoked from within<br>"generate_synth SDRAMController_s0""

The first apparently relevant message in the list is

"Error: Makefile:539: recipe for target 'obj/HAL/src/alt_dcache_flush_all.o' failed"

The "LPDDR2 Controller with UniPHY" uses Nios II for I/O calibration, so it's basicaly the same case as in the first post.