Error: s0: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.b

Hi

Here is the result, but I guess it does not address the original problem I have.

Do you want to send my email to the developer so I can test any patches quicker?

Rebgards

Quartus 19.1, no patch, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: soc_system: Done "soc_system" with 64 modules, 130 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Info (144001): Generated suppressed messages file C:/Users/StefanThorlacius/Downloads/cv_soc_devkit_ghrd_19_1/output_files/soc_system.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 33 warnings
Error: Peak virtual memory: 5126 megabytes
Error: Processing ended: Fri Jul 17 06:33:04 2020
Error: Elapsed time: 00:03:28
Error: Total CPU time (on all processors): 00:03:36

Quartus 19.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: soc_system: Done "soc_system" with 64 modules, 130 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
Error: Peak virtual memory: 5181 megabytes
Error: Processing ended: Fri Jul 17 06:42:22 2020
Error: Elapsed time: 00:00:14
Error: Total CPU time (on all processors): 00:00:13
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings

Quartus 20.1, no patch, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: soc_system: Done "soc_system" with 64 modules, 130 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (169085): No exact pin location assignment(s) for 83 pins of 157 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Error (174068): Output buffer atom "soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination
....
....
....
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
Error: Peak virtual memory: 5182 megabytes
Error: Processing ended: Fri Jul 17 05:24:03 2020
Error: Elapsed time: 00:00:13
Error: Total CPU time (on all processors): 00:00:12
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings

Quartus 20.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: soc_system: Done "soc_system" with 64 modules, 130 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (169085): No exact pin location assignment(s) for 83 pins of 157 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Error (174068): Output buffer atom "soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination
....
....
....
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
Error: Peak virtual memory: 5182 megabytes
Error: Processing ended: Fri Jul 17 05:24:03 2020
Error: Elapsed time: 00:00:13
Error: Total CPU time (on all processors): 00:00:12
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings

Hi

You can see below the result, my guess is that this project do not address the problem I have in our project.

Would it be an idea to pass my email to the developer so we can have fast test and turn around time?

Regards Stefan

Quartus 19.1, no patch, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_ava.....................
Info (144001): Generated suppressed messages file C:/Users/StefanThorlacius/Downloads/cv_soc_devkit_ghrd_19_1/output_files/soc_system.map.smsg
....
....
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 33 warnings

Quartus 19.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_ava.....................
Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
....
....
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings

Quartus 20.1, no patch, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (174068): Output buffer atom ....
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger

Quartus 20.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd

Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis

Project, compile: Failed
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings