Forum Discussion
You may use this design
https://rocketboards.org/foswiki/Documentation/GSRD131CompileHardwareDesign
Check whether emif/hps emif exist there and upgrade the design.
Compile the design in Q20.1 and Q19.1 with patch.
Hi
You can see below the result, my guess is that this project do not address the problem I have in our project.
Would it be an idea to pass my email to the developer so we can have fast test and turn around time?
Regards Stefan
Quartus 19.1, no patch, project cv_soc_devkit_ghrd
Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis
Project, compile: Failed
Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_ava.....................
Info (144001): Generated suppressed messages file C:/Users/StefanThorlacius/Downloads/cv_soc_devkit_ghrd_19_1/output_files/soc_system.map.smsg
....
....
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 33 warnings
Quartus 19.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd
Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis
Project, compile: Failed
Error (12006): Node instance "error_adapter_0" instantiates undefined entity "soc_system_mm_interconnect_0_ava.....................
Error: Quartus Prime Fitter was unsuccessful. 1811 errors, 3 warnings
....
....
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings
Quartus 20.1, no patch, project cv_soc_devkit_ghrd
Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis
Project, compile: Failed
Error (174068): Output buffer atom ....
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger
Quartus 20.1, with patch quartus-19.1std-0.02std-windows, project cv_soc_devkit_ghrd
Platform designer, Generate HDL, Pass
Info: Finished: Create HDL design files for synthesis
Project, compile: Failed
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (293001): Quartus Prime Full Compilation was unsuccessful. 1813 errors, 120 warnings