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Honored ContributorError: Connected system ID hash not found on target at expected base address
Hello,
Usual sentence first: I'm fairly new to FPGA programming, so bear with me. I tried to follow the Nios II Hardware Development Tutorial (version 3.0, Dec. 2009) using the latest (v 11.0) tools (Quartus II, Nios II Tools etc.) on Windows 7. Everything works relatively smoothly (only problem is a timing issue with the JTAG, which I can't solve but can be ignored if I understand correctly). The .sof is written onto the FPGA. It consists of a cpu, onchip_mem, sysid, led_pio (it's a Cyclone III eval board), sys_clk_timer and a jtag uart. The tutorial uses the count_binary sample and everything compiles without error. However, if I try to do Run As -> Nios II Hardware a windows pops open telling me "connected system id hash not found on target at expected base address." If I click System ID Properties I get: Expected system ID base address: 0x11030 (which is the one in the SOPC builder) Expected system ID: 0x0 (which is the one in the SOPC builder) connected system id: not found Expected system timestamp: 1306314921 connected system timestamp: not found I can see the connected USB-Blaster in the Processors and Byte Stream Devices panel. Any suggestions would be much appreciated U.27 Replies
Altera_ForumI understand it I was in the same situation a month back.
Are all the pin connections to the LEDs in the design correct.Verify from the board manual you would have got with the development kit.Because it is a sample design but may be not for your fpga chip pr board?Have you verified all the hardware connections are correct?Did you download the correct .sopc file with correct pin conigurations?Check in the pin planner.- Altera_Forum
Yeah, the pins are correct. I used this configuration for a simple verilog design and it worked. The sopc file is the one created during the tutorial.
Do you know where the "The system console model is invalid. Cannot launch." message comes from? The board or is it a communication error? Do you have a simpler programme that I could test? Just one LED or so? Maybe I'll try to write that myself. - Altera_Forum
- Altera_Forum
The PDF is about a tutorial that doesn't involve the Nios II processor. I know that this would work as I had other verlilog designs running on the test board.
Having read the first thread I tried to download the .elf manually by typing: nios2-download -g count_binary.elf in the Nios II shell. Response: Pausig target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused The second thread contains an unanswered question of you. - Altera_Forum
Check the clocks and resets to your processor. That's normally what causes download failures. Less likely is that your memory system is broken.
- Altera_Forum
There are some critical warnings about timings which didn't meet the specification. I read that I can ignore that as it has something to do with the JTAG. I was unable to solve these timing issues (again my lag of knowledge of FPGA programming etc).
- Altera_Forum
Hi ,
I am posting a design example which did run on my board.It is the complete design with an led but it is for cyclone 3.Modify it according to your fpga and its constraints. Documentation: http://www.altera.com/literature/tt/tt_nios2_hardware_tutorial.pdf - Altera_Forum
Found this one:
nios ii compact design (http://www.altera.com/support/examples/nios2/exm-nios-compact.html) Works fine on the Cyclone III Starter Kit by just following the command line instruction in the tutorial section of the PDF. Still don't know why the other one won't work. - Altera_Forum--- Quote Start --- There are some critical warnings about timings which didn't meet the specification. I read that I can ignore that as it has something to do with the JTAG. I was unable to solve these timing issues (again my lag of knowledge of FPGA programming etc). --- Quote End --- What are the failing paths? You can only ignore those messages if the failing paths are actually in the jtag components.
- Altera_Forum
Since you failed to get the systemID and timestamp, a quite simple thing to complete, there is something wrong with the cpu and memory system. I just figure out the same problem as you have. Here is my experience for reference.
I checked my design carefully and found nothing doubtful, so I wondered why the cpu didn't respond to the PC. Oh, I forgot the reset signal and it was asserted forever by a switch. I flipped the switch and every thing worked. So, figure out why your cpu doesn't respond the systemID inquiry, then you can advance to the next step.
