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Altera_Forum
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19 years ago

DDR2 & Cyclone II EP2C8

edit: to be clear, i mostly want to know: has anyone used ddr2 with an ep2c8 speed grade 8?

I am currently evaluating the possibility of using DDR2 memory, one device with x16 bit wide bus running at 125MHz, on an EP2C8 device with the slowest speed grade (8). Instinct tells me that this might be tricky to manage. App notes and data sheets hint that it's possible.

I tried actually creating a system in SOPC builder with a standard CPU, some normal stuff, and the DDR2 core. Quartus complained loudly during fitting, saying that some "DDIO output nodes" could not be routed.

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

Error: DDIO Node "ddr2_sdram_0:the_ddr2_sdram_0|ddr2_sdram_0_auk_ddr_sdram:ddr2_sdram_0_auk_d

dr_sdram_inst|ddr2_sdram_0_auk_ddr_datapath:ddr_io|ddr2_sdram_0_auk_ddr_dqs_group

:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|ou

tput_cell_L[0]" could not be constrained to a legal location[/b]

--- Quote End ---

etc. There were about 8 of these.

I believe this has to do with the choice of I/O bank used when instantiating the core from SOPC Builder. Buried in one of the app notes, it says that "banks 2 and 4" can be used for DDR2 on the EP2C8. I tried this with a number of combinations and it gave me the exact same errors, which leads me to believe that I&#39;m just not doing something right, or Quartus isn&#39;t noticing my changes correctly.

anyway, I&#39;d like to know if anyone has done this before successfully and what process was used. Thanks!

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    This might be a bug in the DDR/DDR2 SOPC component, I had similar problems with DDR. Use the default name for the instantiated component in sopc builder. I think it is:

    ddr_sdram_0

    the trailing _0 was the problem on my design.

    Iztok Jeras
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    There is another problem implementing Nios + DDR inside a chip as small as the EP2C8. There is not enough space in the chip for timing optimizations so DDR and the processor must run at different clock speeds, which adds latency for DDR access due to crossing clock domains.

    The problem gets even worse, if you want to add a DMA to the design.

    I will try to post details on our project using EP2C8 and DDR (1) when we try a few sopc configurations and benchmark them.

    Iztok Jeras
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by iztok.jeras@Oct 8 2006, 09:57 AM

    there is another problem implementing nios + ddr inside a chip as small as the ep2c8. there is not enough space in the chip for timing optimizations so ddr and the processor must run at different clock speeds, which adds latency for ddr access due to crossing clock domains.

    the problem gets even worse, if you want to add a dma to the design.

    i will try to post details on our project using ep2c8 and ddr (1) when we try a few sopc configurations and benchmark them.

    iztok jeras

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18592)

    --- quote end ---

    --- Quote End ---

    Hi iztok,

    I have 2 questions:

    - what package are you using (TQFP, BGA ?)

    - what is the targetted clock frequency ?

    Regards.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by bigboss25@Oct 9 2006, 09:45 AM

    hi iztok,

    i have 2 questions:

    - what package are you using (tqfp, bga ?)

    - what is the targetted clock frequency ?

    regards.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18599)

    --- quote end ---

    --- Quote End ---

    We did not have a clear target, but I was able to compile a project without DMA at:

    - CPU 60MHz (it may work at up to 75MHz)

    - DDR 110MHz

    I tried to compile a very minimal project (only cpu, ddr, uart) with a common CPU and DDR clock, the minimum frequency for the DDR is about 85MHz and I was able to compile the whole system at 87MHz (as far as I remember). But we did not conduct any tests we probably will.

    IzI
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by bigboss25@Oct 9 2006, 09:45 AM

    hi iztok,

    i have 2 questions:

    - what package are you using (tqfp, bga ?)

    - what is the targetted clock frequency ?

    regards.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18599)

    --- quote end ---

    --- Quote End ---

    TQFP, we do not use BGA yet http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

    but remember, 0804 4-resistors arrays used for parallel and serial termination are too small to solder by hand, we have about 4 soldering errors on each prototype

    IzI
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Any update on how to fix this?

    I&#39;ve the same problem on a cyclone II dev board.

    I&#39;ve instantiated the design via SOPC builder and synthesis fails due to "DDIO output nodes could not be placed by the fitter"

    renaming the ddr_sdram_0 in SOPC builder to ddr_sdram without the trailing "_0" did not fix the problem
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by mgilroy@Oct 9 2006, 02:10 PM

    any update on how to fix this?

    i&#39;ve the same problem on a cyclone ii dev board.

    i&#39;ve instantiated the design via sopc builder and synthesis fails due to "ddio output nodes could not be placed by the fitter"

    renaming the ddr_sdram_0 in sopc builder to ddr_sdram without the trailing "_0" did not fix the problem

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18603)

    --- quote end ---

    --- Quote End ---

    you SHOULD! name the DDR ddr_sdram_0, this was my point (nad NOT! without _0)

    you have a different problem, maybe you did not place the DDR signals to dedicated pins, compare the .qsf file of your project with the .qsf file of the Altera development board, check for:

    - IO block power supplies

    - if DDR pins are SSTL (this should be done automatically by SOPC builder)

    if you find it easier you may use the assignment editor

    IzI
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Apologies, I had miss read that bit. I had originally named the block ddr_sdram_0 I had the same problem then. As far as I can see I have all the same assignments as used by the standard example file.

    Foud the problem. The pin names were wrong for some reason, I&#39;d missed the warning in Quartus. Renamed them to the correct names in assignment editor fixed this problem.