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originally posted by iztok.jeras@Oct 8 2006, 09:57 AM
there is another problem implementing nios + ddr inside a chip as small as the ep2c8. there is not enough space in the chip for timing optimizations so ddr and the processor must run at different clock speeds, which adds latency for ddr access due to crossing clock domains.
the problem gets even worse, if you want to add a dma to the design.
i will try to post details on our project using ep2c8 and ddr (1) when we try a few sopc configurations and benchmark them.
iztok jeras
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Hi iztok,
I have 2 questions:
- what package are you using (TQFP, BGA ?)
- what is the targetted clock frequency ?
Regards.
Honored Contributor
