Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDDR2 & Cyclone II EP2C8
edit: to be clear, i mostly want to know: has anyone used ddr2 with an ep2c8 speed grade 8? I am currently evaluating the possibility of using DDR2 memory, one device with x16 bit wide bus run...
Altera_ForumHonored Contributor
Honored ContributorThere is another problem implementing Nios + DDR inside a chip as small as the EP2C8. There is not enough space in the chip for timing optimizations so DDR and the processor must run at different clock speeds, which adds latency for DDR access due to crossing clock domains.
The problem gets even worse, if you want to add a DMA to the design. I will try to post details on our project using EP2C8 and DDR (1) when we try a few sopc configurations and benchmark them. Iztok Jeras
