What does Arria10 FPLL calibration in core mode do?

We want to use a fractional pll with reconfiguration enabled in order to generate a core clock, synchronized to external timestamps. We use quartus 18.0.0 to generate an fPLL. Our problem is that we are noticing that the pll_cal_busy stays high and pll_locked stays low indefinitely. It looks like the clock on the output is not running.

We tried cycling pll_powerdown. This seemingly has no impact.

We tried triggering regeneration using the sequence in: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/component/2017/why-does-the-fpll-not-lock-with-enable-phase-alignment-option-tu.html

It looks like the FPLL still stays in calibration mode indefinitely.

We found this post on the forum:

https://forums.intel.com/s/question/0D50P00003yyTeySAE/arria-10-fpll-lock-problem?language=en_US

Which looked like a similar issue. Adding to the project file:

set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_DISABLE_RESET_CONNECTED_TO_CAL_BUSY=1"

This did make the clock to start running, the pll_cal_busy stays high and the pll_locked signal stays low. The strange thing is that reading the 0x280 register results in a 0x7, indicating that the PLL is locked.

We use an external clock generator IC as source for the FPLL in an Arria10 SoC FPGA. The output of this IC is configured by the hardware processor after booting. This means that the clock is not available during initial configuration of the FPGA fabric. Could this be an issue? We were assuming that this would be fixed by a pll_powerdown cycle and a recalibration.

We use a ALTCLKCTRL to be able to connect the FPLL ref clock to a normal clock input. Specifically IO_B2A_L13_CLK0_AB16_P of the 10AS027E4F29E3SG.

We would like some pointers on how to continue with the FPLL IP.

What is the impact of ignoring calibration?

Is my FPLL actually in lock or not?

How can we make the calibration actually finish?