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CKlei8's avatar
CKlei8
Icon for New Contributor rankNew Contributor
7 years ago

What does Arria10 FPLL calibration in core mode do?

We want to use a fractional pll with reconfiguration enabled in order to generate a core clock, synchronized to external timestamps. We use quartus 18.0.0 to generate an fPLL. Our problem is that we ...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

ok...i am not sure about the board .but lets try to solve your issues ....Can you tell me which mode you are using the FPLL?

I would like to ask all the details of the FPLL setting in the IP and if could share that ..let me try with one of the board here ..

Thank you ,

Regards,

Sree