Forum Discussion
CKlei8
New Contributor
New ContributorWhat does Arria10 FPLL calibration in core mode do?
We want to use a fractional pll with reconfiguration enabled in order to generate a core clock, synchronized to external timestamps. We use quartus 18.0.0 to generate an fPLL. Our problem is that we ...
SreekumarR_G_Intel
Frequent Contributor
Frequent ContributorMay i know is that custom board or the Intel FPGA development kit ?
if it is dev kit , can you let me know which one ..so that I can create one example design and send to you ?
