What does Arria10 FPLL calibration in core mode do?

Hello Sree,

Thank you for the response and help in solving this issue.

We use the FPLL in core mode as we want to use it as a core clock source. I included a screenshot of the settings I used, and attached a zip file of the fPLL IP.

We convert the AXI bus from the Arria 10 hardware processor to Avalon and map it's range to the memory. The 'pll_powerdown', 'pll_locked' and 'pll_cal_busy' signals are connected to registers in the memory range of AXI bus.

The 'pll_refclk0' is generated from a SI5338 clock generator IC, which is also configured by the processor at boot up. It is set up to generate a 99.585 MHz clock.

Currently, the output 'outclk0' of FPLL is connected to a counter, that toggles an LED every 5000000 clock cycles.

Are you aware that this case was moved/copied to premiersupport.intel.com and was picked up by Pawel Makyla on the 22th of July?