Video Clocked output and VGA

The VIP Test Pattern Generator and the clocked video output will do the work.

The only thing is that you need to connect the Clocked video output signals to the VGA HS and VS of the VGA connector and the data, blank and sync to the D2A on the DE2 board. you can use one of the video example designs that are avalible on this forum.

Goodluck,

Reuven Aboudi

Thanks for your answer.

I've managed to use text pattern and clocked output, no i can display color bars both in 1024*768 and 640*480.

Right now, I am trying to use the frame buffer between the test pattern generator and the clocked video output, using the sdram to store pixels.

I am not sure on wich clock should I use.

Now, I am in trouble with the frame buffer and clocks...

I am using (in 640*480) 31.5 MHz as pixel video clock, 100 MHz as test video, clocked output and frame buffer clock,finally, a 100Mhz with a -3ns delay for the SDRAM, but the system does not work. I have no DDR2 on the DE2 board, but I think that it shouldn't be necessary in order to use the FB with a 640*480 image.

Any hint?

Hi again,

I had difficulty to understand exactly what you have done especially the explanations about clocks.

But I can recommend you that I use the Frame buffer with a different clocks for memory and video stream (the clock of all VIP components), you can this by configuring the FB to "use separate clocks for avalon-MM master interface".

BR,

Reuven

Well,

I am tryng to use buffering for video streams in my system.

To buffer an 640*480 video frame, i need at least 1.2Mb of memory, so i have to use sdram.

This sdram is an SDR (the DE2 has only a 8M SDR sdram), and in a tutorial for the sdram they(Altera) say that sdram need a -3ns delay.

So, my system is this:http://img62.imageshack.us/img62/7727/videotest.png (http://img62.imageshack.us/i/videotest.png/)

But the output is still incorrect, and i don't know why.

and If I use buffer inside the deinterlacer, I have the same troubles...

It looks like that you may have problems are with the SDRAM.

From what I see I think you are working with high clock rates for both the video and memory.

Your video clock is 70MHz while you need for composite input only 27MHz if the color components are parallel the VGA output (640 x 480 @ 60Hz) only need 25 MHz if the color components are parallel. 50 MHz clock for video will be OK.

The SRAM clock you use is 140MHz, but I think the SDRAM controller work only up to 100MHz in Stratix devices, in other device even less.

I would also suggest you to read in the SDRAM Controller document and follow the clock phase setting for the SDRAM.

Good luck,

Reuven

Thanks again for the reply.

The sdram I am using is A2V64s40CTP -G6, wich is said to support 166 Mhz of clock.

I've used slower clocks, such as 25MHz for VGA, 50MHz for vip interfaces and 100MHz for the sdram, but still I can't get a "valid" output.

I used the -3ns delay for the sdram, so IF all this is right, maybe I used the wrong settings for the Avalon-MM master interfaces.

Hi again,

The only way I know to be certain regarding the SDRAM is to evaluate it using the NIOS.

If you are familiar with NIOS development it is very easy to create a simple NIOS design with on chip memory and see that it is working properly.

Then you replace the on chip memory with the SDRAM memory and "play" with the delay between the clock supplied to the SDRAM controller (the clock in the SOPC) and the clock supplied to the SDRAM memory (the output pin from the FPGA the SDRAM clock) till the NIOS Design is working properly.

If you are not familiar with NIOS development you can try "playing" with the delay between the clocks (using the PLL) and see if you get a result but it is not like to NIOS that you know that every thing else is working fine with on chip memory.

Again Good luck!

Reuven

one (last, I hope) more question:

If I want to use ADV7181 with the clocked input megacore function, how sohuld I set the CVI?

I've tried with pal, 8bits for color plane, 2 color planes PAL. The dsata sheed says the output from the adv is YCbCr 4:2:2 8 bits, but all the configurations I've tried didn't work..

Hi,

I worked with the ADV7180 on the Neek board and it worked fine in the way you configured the CVI.

I believe the ADV7181 is the same and there is no need to use the I2C to configure the registers in order to start working in automatic standard detection mode.

BR,

Reuven

quite strange.

i used the video and audio config provided by altera to set up adv7181.

then, settings of my vip CVI should be correct.

here they are:

http://img502.imageshack.us/img502/8623/cvi.png (http://img502.imageshack.us/i/cvi.png/)

and thi is the schematic of my system:

http://img34.imageshack.us/img34/617/schematic.png (http://img34.imageshack.us/i/schematic.png/)

I don-t know why, but STILL it seems to be wrong..

The other components work correctly using a test pattern generator, (8bits, Ycbcr 4:2:2) instead of the clocked input..

suggestions?