Video Clocked output and VGA

Hi again,

The only way I know to be certain regarding the SDRAM is to evaluate it using the NIOS.

If you are familiar with NIOS development it is very easy to create a simple NIOS design with on chip memory and see that it is working properly.

Then you replace the on chip memory with the SDRAM memory and "play" with the delay between the clock supplied to the SDRAM controller (the clock in the SOPC) and the clock supplied to the SDRAM memory (the output pin from the FPGA the SDRAM clock) till the NIOS Design is working properly.

If you are not familiar with NIOS development you can try "playing" with the delay between the clocks (using the PLL) and see if you get a result but it is not like to NIOS that you know that every thing else is working fine with on chip memory.

Again Good luck!

Reuven