VHDL-Code with Avalon Bus Interface-/ and VHDL-Video-System-Interface-Ports

Hello

I provided the following ENTITY. Can I actually provide a IP, which some haven connectivity with the Avalon bus, as well as haven as down descriptive for the VHDL_Detector, which is not connected with the Avalon bus, but with the video system, which was evenly not provided in SopC?

We provide as it were 2 different systems, the Video_System as own symbol and the SopC system also as own symbol.

These 2 different systems can communicate however by the VHDL_Detector via Avalon bus with one another.

-- VHDL_Detector Clock interface

iVGA_CLK : in std_logic;

iRST_N : in std_logic;

-- VHDL_Detector of In-haven

iVGA_R : in std_logic_vector (9 downto 0);

iVGA_VS : in std_logic;

This haven are connected with the video system.

-- Avalon Clock interface

csi_clock : in std_logic;

csi_reset : in std_logic;

-- Avalon mm of interfaces/Slave haven

avs_write : in std_logic;

avs_writedata : in std_logic_vector (31 downto 0);

avs_read : in std_logic;

avs_readdata : out std_logic;

avs_dataavailable : out std_logic;

avs_byteenable : in std_logic_vector (3 downto 0)

This haven are connected with the SopC.

**********************************************************************************

ENTITY ime_avalon_xy_detector IS

PORT

(

-- VHDL_Detector Clock Interface

iVGA_CLK : in std_logic;

iRST_N : in std_logic;

-- VHDL_Detector IN-Ports

iVGA_R : in std_logic_vector(9 downto 0);

iVGA_VS : in std_logic;

-- Avalon Clock Interface

csi_clock : in std_logic;

csi_reset : in std_logic;

-- Avalon-MM Interface / Slave Port

avs_write : in std_logic;

avs_writedata : in std_logic_vector(31 downto 0);

avs_read : in std_logic;

avs_readdata : out std_logic;

avs_dataavailable : out std_logic;

avs_byteenable : in std_logic_vector(3 downto 0)

);

END ENTITY ime_avalon_xy_detector;