Honored ContributorHello,
I hope someone can help me. I want to use the altera TSE as an ethernet connection in a x86-PC-design. I'm using PCIe to connect the FPGA to the CPU and the OS is Linux. The system is like: x86 -> PCIe -> TSE -> Ethernet The kernel (4.9.x) provides an altera TSE-support, but how can I tell him that the TSE is connected via PCIe? :confused::confused: Thanks in advance Chris
Honored ContributorHi Christh,
As per my understanding, the TSE IP is not directly connected to the PCIE. There should have some logic+ memory to process and store the Ethernet Packet, and the root port can issue a memory read or write command via PICE to access memory for the Ethernet data. For example: X86 -> PCIE -> Logic + Memory -> TSE Best Regards, Terence (This message was posted on behalf of Intel Corporation)Honored ContributorHi Terence,
thanks for the hint. I adapted the a TSE reference design with logic + memory. So the Qsys-architecture is like - PCIe Avalon MM | - TSE MAC (control port) | - Scatter Gatter DMA TX --- Avalon ST to TSE transmit | - Scatter Gatter DMA RX --- Avalon ST to TSE receive | - OnchipMem for descriptor memory | - Some PIO The root port is a x86. I have access via the pci-structure to the PIO (some LEDs) and that doing well. Do you know a possiblity to test the TSE only with some memory-settings via PCIe. What information (device tree?) must a kernel know to access the TSE via the structure above? We want to use it as a network device, so we can send a ping for example. Thanks in advance, Chris
Contributorvery interetsing implementation ~
Hi Christh, Had you finished the "TSE w/ PCIe" design? Would you share QSYS diagram for our reference ？
Honored ContributorHi Chris,
To configure the TSE register is via the Avalon MM interface. If you can access the PIO, then you should be able to access the TSE register as well. It is just difference addressing. Regards Terence (This message was posted on behalf of Intel Corporation)
