Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi Terence,
thanks for the hint. I adapted the a TSE reference design with logic + memory. So the Qsys-architecture is like - PCIe Avalon MM | - TSE MAC (control port) | - Scatter Gatter DMA TX --- Avalon ST to TSE transmit | - Scatter Gatter DMA RX --- Avalon ST to TSE receive | - OnchipMem for descriptor memory | - Some PIO The root port is a x86. I have access via the pci-structure to the PIO (some LEDs) and that doing well. Do you know a possiblity to test the TSE only with some memory-settings via PCIe. What information (device tree?) must a kernel know to access the TSE via the structure above? We want to use it as a network device, so we can send a ping for example. Thanks in advance, ChrisJET60200
Contributor
4 years agovery interetsing implementation ~
Hi Christh, Had you finished the "TSE w/ PCIe" design? Would you share QSYS diagram for our reference ?