Using SODIMM DDR2 module on Cyclone 3

You would need 8 x8 DQS groups, which can be supported on the 40F484, (C3 device handbook, table 9-5) but it will take all the IO banks on the two sides of the chip just for DQ groups. The address/command will be on a third side.

So it should fit, but your problem is that it will use the majority of the pins on your chip, and many of the remainder will be forced to a 1.8v IO standard.

The problem is likely to be running out of pins or IO banks to do other useful stuff with, but a quick IO ring design should clear that up.

Another resource to keep an eye on is clocks and clock networks. The rules are compicated and varied so FvM's suggestion of a test design is a good idea if you can.

The PLL-feedback was supported in earlier versions of Quartus and for CycloneII and StratixII. I just checked the MegaWizard and for CycloneIII Altera chose to 'only' deliver the 'advanced' solution (ALTMEMPHY ...). But you're right, doing the PLL approach from scratch will be a big project.

The EP3C40F484 has 16 DQSx8 groups, so rws28 should be able to implement his DIMM interface just using 2 sides, because, to my idea, he can use the non-DQ pins to supply command and address to the DIMM. That would leave the 2 other sides for interfacing logic with a different VccIO voltage.

I am also interested in using a 4GB sodimm w/ the CycloneIII except I will be using the largest CycloneIII EP3C120. When trying to add the hpddr2 controller in sopc builder I get the following errors:

Error: cpu_0: Nios II Instruction Master cannot address memories over 2^32

Error: cpu_0: Nios II Data Master cannot address memories over 2^32

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits

Does this mean that 4GB is not supported? When changing it to a 2GB I part I still get this error:

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits

Only when I change to a 1GB do the errors go away. I really need to use the 4GB sodimm, is there any way around this problem?

Thank you!

Brianna

--- Quote Start ---

I am also interested in using a 4GB sodimm w/ the CycloneIII except I will be using the largest CycloneIII EP3C120. When trying to add the hpddr2 controller in sopc builder I get the following errors:

Error: cpu_0: Nios II Instruction Master cannot address memories over 2^32

Error: cpu_0: Nios II Data Master cannot address memories over 2^32

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits

Does this mean that 4GB is not supported? When changing it to a 2GB I part I still get this error:

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits

Only when I change to a 1GB do the errors go away. I really need to use the 4GB sodimm, is there any way around this problem?

Thank you!

Brianna

--- Quote End ---

These errors are a limitation of the NIOS CPU, not the DDR core. As Phil Wise suggested, an intermediate module with a page register would solve the addressing errors.

The big problem is going to be fitting the controller so it meets timing with the DQ groups placed on opposite sides of the chip(this can be more difficult with a larger FPGA). I know for Stratix and Arria, Altera recommends that the DQ groups be placed on one side or one corner of the chip - this probably applies to Cyclone devices too. As you can see from http://www.altera.com/literature/hb/cyc3/cyc3_ciii51008.pdf, none of the Cyclone III packages offer more than 6 x8 groups per side.

It would be best to instantiate a 4 GB memory controller separately at the speed you want (with the Megawizard, not SOPC builder), create a simple pass-through Avalon interface to the NIOS (just chop off the top bits; paging can be implemented later), pin it out, and run a timing analysis. If it doesn't meet timing, turn on all the fitter optimizations and turn of the placement/fitter effort. If it still doesn't meet timing at the lowest speed that meets your design requirements, you might be out of luck.