Using SODIMM DDR2 module on Cyclone 3

You would need 8 x8 DQS groups, which can be supported on the 40F484, (C3 device handbook, table 9-5) but it will take all the IO banks on the two sides of the chip just for DQ groups. The address/command will be on a third side.

So it should fit, but your problem is that it will use the majority of the pins on your chip, and many of the remainder will be forced to a 1.8v IO standard.

The problem is likely to be running out of pins or IO banks to do other useful stuff with, but a quick IO ring design should clear that up.

Another resource to keep an eye on is clocks and clock networks. The rules are compicated and varied so FvM's suggestion of a test design is a good idea if you can.