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Altera_Forum
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17 years ago

Using SODIMM DDR2 module on Cyclone 3

Hi All, Hope someone can help. I'm just trying to establish the feasibility of using a SODIMM memory DDR2 memory module (e.g Micron MT16HTS25664H) with a Cyclone III FPGA (EP3C40F484C6 o...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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I am also interested in using a 4GB sodimm w/ the CycloneIII except I will be using the largest CycloneIII EP3C120. When trying to add the hpddr2 controller in sopc builder I get the following errors:

Error: cpu_0: Nios II Instruction Master cannot address memories over 2^32

Error: cpu_0: Nios II Data Master cannot address memories over 2^32

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits

Does this mean that 4GB is not supported? When changing it to a 2GB I part I still get this error:

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits

Only when I change to a 1GB do the errors go away. I really need to use the 4GB sodimm, is there any way around this problem?

Thank you!

Brianna

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These errors are a limitation of the NIOS CPU, not the DDR core. As Phil Wise suggested, an intermediate module with a page register would solve the addressing errors.

The big problem is going to be fitting the controller so it meets timing with the DQ groups placed on opposite sides of the chip(this can be more difficult with a larger FPGA). I know for Stratix and Arria, Altera recommends that the DQ groups be placed on one side or one corner of the chip - this probably applies to Cyclone devices too. As you can see from http://www.altera.com/literature/hb/cyc3/cyc3_ciii51008.pdf, none of the Cyclone III packages offer more than 6 x8 groups per side.

It would be best to instantiate a 4 GB memory controller separately at the speed you want (with the Megawizard, not SOPC builder), create a simple pass-through Avalon interface to the NIOS (just chop off the top bits; paging can be implemented later), pin it out, and run a timing analysis. If it doesn't meet timing, turn on all the fitter optimizations and turn of the placement/fitter effort. If it still doesn't meet timing at the lowest speed that meets your design requirements, you might be out of luck.