usage of SGDMA IP for data transfer to and from DDR3

Question

Hi,I want to develop a system with NIOS II Processor on Arria V of one of our custom boards  for DDR3 memory transfers.where as there will be a sensor which will be giving around 128 bit data per clock cycle, and that data we want to transfer to DDR3 on our board itself using SGDMA and NIOS II processor and after that we wanted to read the data also from DDR3 using NIOS II and SGDMA to a USB connection which is connected to FPGA.Can you help us in finding a sample design in this point of view where as data transfer happens using SGDMA and NIOS II between FPGA and DDR3?Its been important for us to complete this but couldn't able to find any correct design as example for this as starting point to us.By the way I am new to quartus where as our previous development used to go with Xilinx(vivado).Please help us in fastening our development process by providing some useful tutorials and links to solve the above mentioned task.

nuraida_a_intel · Answer

Hi,Also you may refer to Intel FPGA wiki that consist some generic MSGDMA and EMIF design. Hope this helps.ThanksRegards,NAli1

nuraida_a_intel · Answer

Dear Vsath1,Please allow me some time to look into your issue. I shall come back to you with finding. Thank you for your patience. Regards,NAli1

nuraida_a_intel · Answer

Hi Vsath1,I can give you idea on how to debug the issue. I will suggest you signaltap (stp) the avalon-MM interface (interface between DDR3 and MSGDMA) and check which signal is not behave unexpected. You can compare the stp waveform with the working design like NIOS II to DDR3. ThanksRegards,NAli1

nuraida_a_intel · Answer

Hi VSath1, Just to let you know that we are still working on the design to isolate the root cause. I'll let you know the results once we have done. Thanks.Regards,NAli1