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Hi Vsath1,
I can give you idea on how to debug the issue. I will suggest you signaltap (stp) the avalon-MM interface (interface between DDR3 and MSGDMA) and check which signal is not behave unexpected. You can compare the stp waveform with the working design like NIOS II to DDR3.
Thanks
Regards,
NAli1
- VenkateshSathar6 years ago
Occasional Contributor
yes.. I will look in that way also and tell you if anything I find.. meanwhile please review the project I have sent and if possible if you have the kit i mentioned you also run once and see the result please. Actually I already enable signal tap also in the project i gave. You can see that also once.
- NurAida_A_Intel6 years ago
Frequent Contributor
Hi VSath1,
Just to let you know that we are still working on the design to isolate the root cause. I'll let you know the results once we have done.
Thanks.
Regards,
NAli1
- VenkateshSathar6 years ago
Occasional Contributor
Hi NAli1,
Very nice to hear that from that.
Have to tell one good news. After enabling Signal tap found that there is no transfer happening from NIOS to DDR where as transfer from MSGDMA to DMA is happening and that is because accidentally the DATA_BUS of NIOS is not connected to DDR3_CONTROLLER's AVALON_BUS. Corrected that and generated a new .sof file and then that point onwards it started working. Thanks for the help of giving the idea to solve the problem using signal tap. It helped us.
Regards,
Venkatesh Sathar.
- NurAida_A_Intel6 years ago
Frequent Contributor
Hi Venkatesh,
Thanks you for sharing the good news and I'm glad to hear that everything is working now at your side now. 😊
You are more than welcome. Feel free to post any update in Intel Forum if you encounter any issue in future. We will try our best to support you.
Thanks and have a nice day !
Regards,
NAli1