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Occasional ContributorTX sync header error insertion in Arria 10 GX
Hi,
I have a problem regarding Tx error insertion function on Arria 10 GX 10GBASE-R with FEC.
I have built two duplex 10GBASE-R with FEC PHYs on my board, connecting Tx to Rx through DAC cable.
Packet Transmit and receive test is working good by viewing Rx stream port by Signal Tap.
For error insertion test, I have set "Enable TX sync header error insertion" option in the parameter editor, and I drove the tx_err_ins PHY input port.
But I have no Rx stream change after error insertion.
In my thought, by receiving corrupted sync header in the RX, the rx_enh_blk_lock output port would go low.
Do you have any method to confirm sync header error was inserted in the TX encoder?
In another point, I have unclear description in the user guide:
Table 24. 64b/66b Encoder and Decoder Parameters on Page 60,
---
"Enable TX sync header error insertion"
When you turn on this option, the Enhanced PCS supports cycleaccurate error creation to assist in exercising error condition testing on the receiver.
When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly.
If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.
---
I can't find what "the error flag" is.
Thank you for any help.
20 Replies
ZiYing_IntelFrequent Contributor
Hi MamaSaru,
You can check sync header error through the status of the PCS sync header output by encode in PCS.
Besides that, the error flag here means the sync header error.
Best regards,
zying
MamaSaruHi zying,
Thank you for your help.
>You can check sync header error through the status of the PCS sync header output by encode in PCS.
Can you teach me exact output signal name of the IP?
>Besides that, the error flag here means the sync header error.
Do you mean the error flag is the internal signal of the IP?
Regards,
- ZiYing_Intel
Hi MamaSaru,
Do you still have any question about this issue?
Best regards,
zying
- ZiYing_Intel
Hi,
You may check the sync header error status under the PCS> encode>sync_out in the simulation file.
The error flag means the sync header error. The CRC is inserted in the last 4 bytes of the frame (user data) by MAC block. Then, user data is sent to TX PCS, where 64B/66B operation is done. After this, the sync header error is added in the PCS block.
Best regards,
zying
- MamaSaru
Did you send any files?
- ZiYing_Intel
Hi,
I got send a picture. Caen you see it?
Best regards,
zying
- MamaSaru
No, I am sorry that no picture is displayed in your post.
I am reffering Intel Arria 10 Transceiver PHY User Guide 2023.09.15.
Pointing out somewhere from this doccument is helpfull.
If you need other document or file for explanation, please send me the file instead of the screenshot.
- ZiYing_Intel
Hi,
You may check the sync header error status under the PCS> encode>sync_out in the your design simulation file.
Best regards,
zying
- MamaSaru
You misunderstand my intentions in the following two points.
1. I am not in simulation but in real A10 design.
2. I would like to check received syn header is corrupted at Rx side. - ZiYing_Intel
Hi,
Sorry for the delay in response. I am checking it with my internal team and will get back to you with findings.
Best regards,
zying
- ZiYing_Intel
Hi MamaSaru,
Q1. Error Insertion on Sync Header
>> You are suggested to use C.0x089 bit[5] to insert error on sync header in the TX-path. Error happens once on every rising edge of C.0x089 bit[5] setting (0->1).
The "tx_err_ins" is control signal for Interlaken block, so it should not be used in this case.
For further information, you may refer to the Arria 10 Transceiver Register Map in the Arria 10 Transceiver PHY User Guide, Section 6.19, pg 575, https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-register-map.html
Q2. How to check received syn header is corrupted at Rx side?
>> If the sync header of received 66B data is broken, it cannot be detected as data/control word. Then, it is consequently detected as CRC error and it may be dropped and identified CRC error or frame error.
It would be reflected to receiver statistics counter.
You can read receiver statistics counter registers.
Best regards,
zying
- MamaSaru
Hi zying,
For Q1:
I could find sh_err bit in the Extended Register Map as you suggested.
But I have no register access path for the register because I do not need to reconfigure the PHY.
In my opinion, adding the AND gate after the sh_err register bit is good for user in case that header error insertion logic is kicked by the rising edge of the sh_err register bit.
The tx_err_ins signal is usable with "Enable KR-FEC TX error insertion" option for FEC block.
The same usability of the tx_err_ins signal would be expected for 64b/66b encoder block.
I have to give it away the sync header error insertion test for now.For Q2:
OK, I understand.Thank you for you help.
My last question:
---
In another point, I have unclear description in the user guide:
Table 24. 64b/66b Encoder and Decoder Parameters on Page 60,
"Enable TX sync header error insertion"
When you turn on this option, the Enhanced PCS supports cycleaccurate error creation to assist in exercising error condition testing on the receiver.
When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly.
If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.
---
What "error flag" is in this description?MamaSaru
- ZiYing_Intel
Hi MamaSaru,
The error flag means the sync header error. The CRC is inserted in the last 4 bytes of the frame (user data) by MAC block. Then, user data is sent to TX PCS, where 64B/66B operation is done. After this, the sync header error is added in the PCS block.
Best regards,
zying
