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MamaSaru's avatar
MamaSaru
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

TX sync header error insertion in Arria 10 GX

Hi, I have a problem regarding Tx error insertion function on Arria 10 GX 10GBASE-R with FEC. I have built two duplex 10GBASE-R with FEC PHYs on my board, connecting Tx to Rx through DAC cable. Pa...
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ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi MamaSaru,

Q1. Error Insertion on Sync Header

>> You are suggested to use C.0x089 bit[5] to insert error on sync header in the TX-path. Error happens once on every rising edge of C.0x089 bit[5] setting (0->1).

The "tx_err_ins" is control signal for Interlaken block, so it should not be used in this case.

For further information, you may refer to the Arria 10 Transceiver Register Map in the Arria 10 Transceiver PHY User Guide, Section 6.19, pg 575, https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-register-map.html

Q2. How to check received syn header is corrupted at Rx side?

>> If the sync header of received 66B data is broken, it cannot be detected as data/control word. Then, it is consequently detected as CRC error and it may be dropped and identified CRC error or frame error.

It would be reflected to receiver statistics counter.

You can read receiver statistics counter registers.

Best regards,

zying