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MamaSaru's avatar
MamaSaru
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

TX sync header error insertion in Arria 10 GX

Hi, I have a problem regarding Tx error insertion function on Arria 10 GX 10GBASE-R with FEC. I have built two duplex 10GBASE-R with FEC PHYs on my board, connecting Tx to Rx through DAC cable. Pa...
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ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi MamaSaru,


The error flag means the sync header error. The CRC is inserted in the last 4 bytes of the frame (user data) by MAC block. Then, user data is sent to TX PCS, where 64B/66B operation is done. After this, the sync header error is added in the PCS block.


Best regards,

zying