TX sync header error insertion in Arria 10 GX

Hi zying,

For Q1:
I could find sh_err bit in the Extended Register Map as you suggested.
But I have no register access path for the register because I do not need to reconfigure the PHY.
In my opinion, adding the AND gate after the sh_err register bit is good for user in case that header error insertion logic is kicked by the rising edge of the sh_err register bit.
The tx_err_ins signal is usable with "Enable KR-FEC TX error insertion" option for FEC block.
The same usability of the tx_err_ins signal would be expected for 64b/66b encoder block.
I have to give it away the sync header error insertion test for now.

For Q2:
OK, I understand.

Thank you for you help.

My last question:
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In another point, I have unclear description in the user guide:
Table 24. 64b/66b Encoder and Decoder Parameters on Page 60,
"Enable TX sync header error insertion"
When you turn on this option, the Enhanced PCS supports cycleaccurate error creation to assist in exercising error condition testing on the receiver.
When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly.
If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.
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What "error flag" is in this description?

MamaSaru