Hi Guys, I'm using 2x DE2-115s with my own Ethernet design (RGMII) and i'm suspecting i'm getting timing issues. I have no real idea on how to set up constraints and i'm just trying to patch something together and i need some help. I'm trying to follow the instructions in the TSE_MAC manual (see attached). In short: ANything i do to the SDC file gets overwritten on compile. The manual says edit the TCL file aswell but i can't see what you would edit there. The TSE manual (page 28, see attached screenie) discusses the generated sdc file and how you have to rename signals. The default being: # *************************************************************# Customer modifiable constraints, value is set default by constraints# *************************************************************# Hierarchical path to the TSE set SYSTEM_PATH_PREFIX ""# Frequency of network-side interface clocks or reference clocks set TSE_CLOCK_FREQUENCY "125 MHz"# Frequency of FIFO data interface clocks set FIFO_CLOCK_FREQUENCY "100 MHz"# Frequency of control and status interface clock set DEFAULT_SYSTEM_CLOCK_SPEED "66 MHz" # Name the clocks that will be coming into the tse core named changed from top level set TX_CLK "tx_clk" set RX_CLK "rx_clk" set CLK "clk" set FF_TX_CLK "ff_tx_clk" set FF_RX_CLK "ff_rx_clk" set TBI_TX_CLK "tbi_tx_clk" set TBI_RX_CLK "tbi_rx_clk" set REF_CLK "ref_clk" If i change the SDC it just gets overwitten. how do i set these up correctly? below is the details of my design we many need to know. ------------------------------------------------------------------------------------------- I am feeding my TSE_MAC with botha firmware data path and a Nios datapath through MUX and DeMUX My Nios is running at 100Mhz. As pictured my TSE_MAC is running all 3 clocks at 50MHz.

Hi, I find this thread very interesting because every time I try to constrain complex designs it goes in a fight between me and the design tool. I think it's because in altera documentation there is a lack that beginners cannot find and learn themselves. I'm not able to find a very basic document explaining what the designer must specify to make QUARTUS doing the rigth fitting and analysis. I believe QII and TQTiming Analyzer are so powerful that "old- fashioned" designers get lost moving from simple and low-level designs to more complex designs using IPs. Let's think to the case of this thread, I did something similar some weeks ago. My design works and Timing Quest Analyzer makes me confident that design is correctly constrained, but my workflow was different from the one depicted here. I didn't modify the <varaition_name>_constraints.sdc:eek: I simply constrained RGMII outputs and inputs at the top level to their respective clocks referring to the AN433: Constraining and Analyzing Source -Synchronous interfaces. RGMII is a source synchronous ddr interface, upon your PHY settings you have to understand if "clock delays" are used or not so in one case you have to refer to the "edge aligned data" scheme or "center aligned data" scheme. I strongly recomend to spend some time trying to understand what you are going "to say" when you write an SDC command. I've already spent to much time trying to copy and paste commands from examples and ANs but the success is a random variable using this approach. I also recomend to read AN477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs. IMPORTANT: Don't rely on the suspect that timing is not met, you have to be sure that your design is fully constrained(clocks, data inputs, dataoutputs) then be sure if your timing are met or not. PLEASE i think It would be very useful to many designers if an expert could comment this thread and/or post link that can help. Thanks a lot.

Thank you very much for the reply. I really wish i had the time to go over it, but i have 12 days to get my thing presentable for my university final mark. Are you able to PM or post the values you have found and are using; this will give me a base to start at. Word can't express my gratitude if your to do so.

let's try. Wich PHY you are using? Can you post a screen shot of you connection from fpga pins to NIOS symbol (graphical)? Anyway, thrust me, AN477 is avery short AN that you must read. It's only 16 pages.

Graphically is a little hard. I've tried to get the RTL viewr to filter from my pins. Attached is a PNG and an XPS in a zip. Both are the same, hopefully they are readable for you. If your after specifics or you want me to do a series of RTL images i will. phy: Marvell 88E1111-CAA1 My actual connected signals are ALL are prefixed with "ENET0_": inputs: RX_CLK RX_DV RX_DATA[3..0] outputs: TX_DATA[3..0] TX_EN RST_N MDC GTX_CLK

I've attached another zip to this post. It has : MySDC file (not the tse_mac one) Multicorner Summary (seems to be a summary of all clock timing results?) Unconstrained paths totals Clocks from timequest. 2 of the red ones are actually states for my avalon ST packet components. Again, thank you

TSE_MAC and Timing Constraints | Altera Community

14 Replies

Altera_Forum
Honored Contributor
14 years ago
Hi,
I find this thread very interesting because every time I try to constrain complex designs it goes in a fight between me and the design tool. I think it's because in altera documentation there is a lack that beginners cannot find and learn themselves. I'm not able to find a very basic document explaining what the designer must specify to make QUARTUS doing the rigth fitting and analysis. I believe QII and TQTiming Analyzer are so powerful that "old- fashioned" designers get lost moving from simple and low-level designs to more complex designs using IPs.
Let's think to the case of this thread, I did something similar some weeks ago. My design works and Timing Quest Analyzer makes me confident that design is correctly constrained, but my workflow was different from the one depicted here. I didn't modify the <varaition_name>_constraints.sdc:eek:
I simply constrained RGMII outputs and inputs at the top level to their respective clocks referring to the AN433: Constraining and Analyzing Source -Synchronous interfaces. RGMII is a source synchronous ddr interface, upon your PHY settings you have to understand if "clock delays" are used or not so in one case you have to refer to the "edge aligned data" scheme or "center aligned data" scheme. I strongly recomend to spend some time trying to understand what you are going "to say" when you write an SDC command. I've already spent to much time trying to copy and paste commands from examples and ANs but the success is a random variable using this approach.
I also recomend to read AN477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs.
IMPORTANT: Don't rely on the suspect that timing is not met, you have to be sure that your design is fully constrained(clocks, data inputs, dataoutputs) then be sure if your timing are met or not.
PLEASE i think It would be very useful to many designers if an expert could comment this thread and/or post link that can help.
Thanks a lot.
Altera_Forum
Honored Contributor
14 years ago
Thank you very much for the reply. I really wish i had the time to go over it, but i have 12 days to get my thing presentable for my university final mark.
Are you able to PM or post the values you have found and are using; this will give me a base to start at. Word can't express my gratitude if your to do so.
Altera_Forum
Honored Contributor
14 years ago
let's try. Wich PHY you are using? Can you post a screen shot of you connection from fpga pins to NIOS symbol (graphical)?
Anyway, thrust me, AN477 is avery short AN that you must read. It's only 16 pages.
Altera_Forum
Honored Contributor
14 years ago
Graphically is a little hard. I've tried to get the RTL viewr to filter from my pins. Attached is a PNG and an XPS in a zip. Both are the same, hopefully they are readable for you.
If your after specifics or you want me to do a series of RTL images i will.

phy: Marvell 88E1111-CAA1

My actual connected signals are ALL are prefixed with "ENET0_":

inputs:
RX_CLK
RX_DV
RX_DATA[3..0]

outputs:
TX_DATA[3..0]
TX_EN
RST_N
MDC
GTX_CLK
RGMII.zip1 MB
Altera_Forum
Honored Contributor
14 years ago
I've attached another zip to this post.
It has :
MySDC file (not the tse_mac one)
Multicorner Summary (seems to be a summary of all clock timing results?)
Unconstrained paths totals
Clocks from timequest. 2 of the red ones are actually states for my avalon ST packet components.
Again, thank you
Addtional.zip252 KB
Altera_Forum
Honored Contributor
14 years ago
I've also had problems using RGMII, but I've taken sdc examples from ethernet example (or it was udp offload example, can't remember) to Cyclone III development kit. Basically, it is important to define all clocks.

Did You add additional PHY initialization files for MAC driver to the Nios project?
Altera_Forum
Honored Contributor
14 years ago
Hey Socrates,
Since my PHY was one of the supported chips I thought I didn't have too add any chip specific stuff. My chip is in the list on page 140 of the tse manual. I have no specific software added in nios for my chip. Am I missing something?
Altera_Forum
Honored Contributor
14 years ago
RGMII is not the default configuration used by the TSE driver. You have to add a file in the NIOS code (SW) to force the driver to set RGMII. I cannot retrieve the details so fast but the solution is somewhere in the forum.

Can you describe what's your problem? What are you able to verify and what not? Do you have an output console to show?
Altera_Forum
Honored Contributor
14 years ago
The situation is described in Altera Knowledge base (source snippet is also included). OR You can do it simpler:
Create web server or simple socket server example project from Nios EDS examples list. Expand the project tree and copy tse_my_system.c (afaik it's called like that) file to Your project directory. Nothing more to be done - compile and it should work.
Altera_Forum
Honored Contributor
14 years ago
Thank you to you all.

Before this post my design works, it just some times, not all the time won't pass DHCP or gets no "free_rx buffers".

The TSE_MAC is configured in QSys to be RGMII. Below is my console print, as you can see it detects my PHY and it works for the most part.

For those following in the future:
I have now followed Socrates excellent suggestion and used an example EDS project and took its "tse_my_system.c" (Note do not do a# include for it, just place it in project).
This has now added the following quote into my original console print from below:

--- Quote Start ---
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
--- Quote End ---

Now i will see how this goes. I also had a look of Socrates suggestion of looking at SDC files from other projects. The UDP offload example cannot have it quartus project expanded without old 9.0 quartus but i dide find some SDC files. Its a little difficult for me to determine what my design needs exactly in comparison to these. For the moment i'm going to see how my design continues and if i have further trouble, i'll have to try figure this out.

fyi: terasic have acknowledged that my board may be faulty, they are testing my design on their boards now to be sure. this is why i'm attempting to use the 2nd ethernet port and continue for the moment without delving too deeply into the more advanced timing constraints i may need.

--- Quote Start ---

PHY INFO: [phyid] 0x11 141 cc2
PHY INFO: Issuing PHY Reset
PHY INFO: waiting on PHY link...
PHY INFO: PHY link detected, allowing network to start.

SSS INFO: Connecting...

InterNiche Portable TCP/IP, v3.1
Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
[get_mac_addr] Checking for MODE config from SW[10] and SW[12].
One and only one must be on to continue start up.
Valkyrie Mode set to Transmitter.
Using Hard Coded MAC Address.
Your Ethernet MAC address is 00:02:02:84:ad:12
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x0c442000
INFO : PHY Marvell 88E1111 found at PHY address 0x11 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link established
INFO : PHY[0.0] - Speed = 1000, Duplex = Full
OK, x=0, CMD_CONFIG=0x00000000
MAC post-initialization: CMD_CONFIG=0x0400020b
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
mctest init called
IP address of et1 : 10.0.0.1
Created "Inet main" task (Prio: 2)
Created "clock tick" task (Prio: 3)
Acquired IP address via DHCP client for interface: et1
IP address : 192.168.1.100
Subnet Mask: 255.255.255.0
Gateway : 192.168.1.1
Valkyrie Nios II Ethernet Socket Server starting up.
Created "monitor_phy" task (Prio: 9)
Created "Valkyrie Platform Heart-Beat uCOS Task" task (Prio: 10)
Created "Valkyrie TCP Ethernet for Commands" task (Prio: 11)
[ResetSocketConnection] Reset Socket Connection Called
[TCP_ServerTask] TCP Server in TX Mode, listening on port 30

--- Quote End ---

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TSE_MAC and Timing Constraints

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