TSE_MAC and Timing Constraints

Hi,

I find this thread very interesting because every time I try to constrain complex designs it goes in a fight between me and the design tool. I think it's because in altera documentation there is a lack that beginners cannot find and learn themselves. I'm not able to find a very basic document explaining what the designer must specify to make QUARTUS doing the rigth fitting and analysis. I believe QII and TQTiming Analyzer are so powerful that "old- fashioned" designers get lost moving from simple and low-level designs to more complex designs using IPs.

Let's think to the case of this thread, I did something similar some weeks ago. My design works and Timing Quest Analyzer makes me confident that design is correctly constrained, but my workflow was different from the one depicted here. I didn't modify the <varaition_name>_constraints.sdc:eek:

I simply constrained RGMII outputs and inputs at the top level to their respective clocks referring to the AN433: Constraining and Analyzing Source -Synchronous interfaces. RGMII is a source synchronous ddr interface, upon your PHY settings you have to understand if "clock delays" are used or not so in one case you have to refer to the "edge aligned data" scheme or "center aligned data" scheme. I strongly recomend to spend some time trying to understand what you are going "to say" when you write an SDC command. I've already spent to much time trying to copy and paste commands from examples and ANs but the success is a random variable using this approach.

I also recomend to read AN477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs.

IMPORTANT: Don't rely on the suspect that timing is not met, you have to be sure that your design is fully constrained(clocks, data inputs, dataoutputs) then be sure if your timing are met or not.

PLEASE i think It would be very useful to many designers if an expert could comment this thread and/or post link that can help.

Thanks a lot.