Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

TSE_MAC and Timing Constraints

Hi Guys, I'm using 2x DE2-115s with my own Ethernet design (RGMII) and i'm suspecting i'm getting timing issues. I have no real idea on how to set up constraints and i'm just trying to patch s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I've attached another zip to this post.

It has :

  • MySDC file (not the tse_mac one)

  • Multicorner Summary (seems to be a summary of all clock timing results?)

  • Unconstrained paths totals

  • Clocks from timequest. 2 of the red ones are actually states for my avalon ST packet components.

Again, thank you