Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

TSE_MAC and Timing Constraints

Hi Guys, I'm using 2x DE2-115s with my own Ethernet design (RGMII) and i'm suspecting i'm getting timing issues. I have no real idea on how to set up constraints and i'm just trying to patch s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Graphically is a little hard. I've tried to get the RTL viewr to filter from my pins. Attached is a PNG and an XPS in a zip. Both are the same, hopefully they are readable for you.

If your after specifics or you want me to do a series of RTL images i will.

phy: Marvell 88E1111-CAA1

My actual connected signals are ALL are prefixed with "ENET0_":

inputs:

RX_CLK

RX_DV

RX_DATA[3..0]

outputs:

TX_DATA[3..0]

TX_EN

RST_N

MDC

GTX_CLK