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I managed to make the gigabit ethernet working on the Cyclone III dev kit with the following:
- connect the rx_clk to the TSE
- use a pll to generate the 125MHz for the transmit clock: phase 0 degres for the TSE, and phase 90 degres for the phy gxt_clk.
- fully constraining all the rgmii pins.
Here are parts of my SDC file. I'm not a Timequest expert either, but I managed to get the interface fully constrained using this, and the design works. You may have to change a few names in the file.
#**************************************************************
# Create Clock
# **************************************************************
create_clock -name {clkin_125} -period 8
create_clock -name {enet_rx_clk} -period 8
# **************************************************************
# Create Generated Clock
# **************************************************************
derive_pll_clocks
set enet_tx_in_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk
set enet_tx_out_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk
# **************************************************************
# Set Input Delay
# **************************************************************
set_input_delay -clock enet_rx_clk -min 1.5 enet_rx_dv}] -add_delay
set_input_delay -clock enet_rx_clk -max 2.5 enet_rx_dv}] -add_delay
set_input_delay -clock enet_rx_clk -clock_fall -min 1.5 enet_rx_dv}] -add_delay
set_input_delay -clock enet_rx_clk -clock_fall -max 2.5 enet_rx_dv}] -add_delay
# **************************************************************
# Set Output Delay
# **************************************************************
set_output_delay -clock $enet_tx_out_clk -max 1 enet_tx_en}]
set_output_delay -clock $enet_tx_out_clk -min -1 enet_tx_en}] -add_delay
set_output_delay -clock $enet_tx_out_clk -clock_fall -max 1 enet_tx_en}] -add_delay
set_output_delay -clock $enet_tx_out_clk -clock_fall -min -1 enet_tx_en}] -add_delay
# **************************************************************
# Set Clock Groups
# **************************************************************
set_clock_groups -exclusive -group
set_clock_groups -exclusive -group
# **************************************************************
# Set False Path
# **************************************************************
set_false_path -from
set_false_path -to
set_false_path -setup -rise_from $enet_tx_in_clk -fall_to $enet_tx_out_clk
set_false_path -setup -fall_from $enet_tx_in_clk -rise_to $enet_tx_out_clk
set_false_path -hold -rise_from $enet_tx_in_clk -rise_to $enet_tx_out_clk
set_false_path -hold -fall_from $enet_tx_in_clk -fall_to $enet_tx_out_clk
# **************************************************************
# Set Multicycle Path
# **************************************************************
set_multicycle_path -from $enet_tx_in_clk -to $enet_tx_out_clk -setup -start 2
# **************************************************************
# Set Maximum Delay
# **************************************************************
set_max_delay -from $enet_tx_out_clk -to 20
# **************************************************************
# Set Minimum Delay
# **************************************************************
set_min_delay -from $enet_tx_out_clk -to 0
The hardest part is to constrain the ddr interface. I'm still not sure I'm doing it right here, but now that it works, I don't want to change it ;)
I'm still amazed that Altera isn't providing a reference design for the Ethernet interface on this development kit... I lost a tremendous amount of time on this (but on the other hand I learned a lot about Timequest!)
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Really thanks for the answering, but my design still does not work.
I am using tse_mac in rgmii mode with 88e1111 phy device.
I "connect the rx_clk to the TSE, use a pll to generate the 125MHz for the transmit clock: phase 0 degres for the TSE, and phase 90 degres for the phy gxt_clk." as you said. I am new for fpga, so i do not know how to use the SDC file.
If it is necessary to add the SDC file when compiling?
Honored Contributor
