TSE generated constraints ignored

Just a couple bits I can answer, with the 'I'm not an expert' disclaimer:

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..."Warning: clk could not be matched with a keeper."

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The warning you're getting is due to get_keepers, which will only find node names that don't get synthesized away. Simply define the rx & tx clocks using port names from the top-level, as shown by daixiwen.

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...Should I be taking the RGMII RX clock from the PHY through a pll/global routing, or just feed the signal directly into the rx_clk port on the TSE?

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The rx_clk pin can be directly fed to the TSE, no need for a pll.