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Altera_Forum
Honored Contributor
Honored ContributorTSE generated constraints ignored
I am having some basic problems with the TSE core, and I'm pretty sure it has to do with timing constraints and/or the actual clocks I'm providing the to the TSE. None of the constraints in the SDC ...
Altera_ForumHonored Contributor
Honored ContributorTry taking rx clock from PHY through pll with -100 degree phase shift and skew tx clock with 100 degree. Also make sure you are giving proper clock to phy as per ethernet link established (i.e. 2.5 MHz for 10Mbps, 25MHz for 100Mbps and 125 MHz for 1000Mbps). You probably need to pass tx/gtx clock to phy through a mux to select appropriate clock depending on your mode selection.
