Tristate Bridge between 32-bit and 16-bit data bus

This seems odd. The problem is most likely between your tristate bridge and MRAM controller. Did you write the MRAM controller? What data width did you use? Did you include byte enables?

Jake

Hello Jake,

Thanks for trying to help me. I did not write the MRAM controller, it just consists of an Avalon-MM interface with fixed wait states.

Here are the settings for this interface:

add_interface mram avalon_tristate end

set_interface_property mram activeCSThroughReadLatency false

set_interface_property mram bridgesToMaster ""

set_interface_property mram holdTime 0

set_interface_property mram isMemoryDevice true

set_interface_property mram isNonVolatileStorage false

set_interface_property mram maximumPendingReadTransactions 0

set_interface_property mram printableDevice false

set_interface_property mram readLatency 0

set_interface_property mram readWaitStates 3

set_interface_property mram readWaitTime 3

set_interface_property mram setupTime 1

set_interface_property mram timingUnits Cycles

set_interface_property mram writeWaitStates 3

set_interface_property mram writeWaitTime 3

set_interface_property mram ENABLED true

add_interface_port mram mram_oe_n read_n Input 1

add_interface_port mram mram_we_n write_n Input 1

add_interface_port mram mram_be_n byteenable_n Input 2

add_interface_port mram mram_address address Input 20

add_interface_port mram mram_data data Bidir 16

add_interface_port mram mram_cs_n chipselect_n Input 1

To answer your questions: yes I included byte enables, and the data width at the MRAM interface is 16 bits.

I will check the signal waveforms at the tristate side to check if the 32-bit words are properly written to the tristate bridge.

I will let you know if something comes out.

Regards,

Florian B.

Sorry, I made some mistakes in my first post. Actually, when the CPU performs a 32-bit write request, two 16-bit write requests are performed by the tristate bridge. The issue occurs when a custom component performs a 32-bit write request to the MRAM. In this case, only one 16-bit write request is performed by the tristate bridge.

Do you know why?

After using the RTL viewer of my project, I can see that at the input of my tristate bridge, the slave writedata bus is only 16 bits wide.

Between my 32-bit NIOS cpu and the tristate bridge, the 32-bit data bus to 16-bit data bus conversion is made by a "cpu_data_master_arbitrator", but the "write" request signal is not processed by this arbitrator.

In the same manner, between my custom master component, called "scope_controller", and the tristate, the 32-bit data bus to 16-bit data bus conversion is made by a "scope_controller_m1_arbitrator", which does not process the "write" request signal also.

Therefore, my guess is that the master component connected to the tristate has to handle the write/read features regarding the data bus width of the slave component.

Do you agree with this statement?