Tristate Bridge between 32-bit and 16-bit data bus

Hello Jake,

Thanks for trying to help me. I did not write the MRAM controller, it just consists of an Avalon-MM interface with fixed wait states.

Here are the settings for this interface:

add_interface mram avalon_tristate end

set_interface_property mram activeCSThroughReadLatency false

set_interface_property mram bridgesToMaster ""

set_interface_property mram holdTime 0

set_interface_property mram isMemoryDevice true

set_interface_property mram isNonVolatileStorage false

set_interface_property mram maximumPendingReadTransactions 0

set_interface_property mram printableDevice false

set_interface_property mram readLatency 0

set_interface_property mram readWaitStates 3

set_interface_property mram readWaitTime 3

set_interface_property mram setupTime 1

set_interface_property mram timingUnits Cycles

set_interface_property mram writeWaitStates 3

set_interface_property mram writeWaitTime 3

set_interface_property mram ENABLED true

add_interface_port mram mram_oe_n read_n Input 1

add_interface_port mram mram_we_n write_n Input 1

add_interface_port mram mram_be_n byteenable_n Input 2

add_interface_port mram mram_address address Input 20

add_interface_port mram mram_data data Bidir 16

add_interface_port mram mram_cs_n chipselect_n Input 1

To answer your questions: yes I included byte enables, and the data width at the MRAM interface is 16 bits.

I will check the signal waveforms at the tristate side to check if the 32-bit words are properly written to the tristate bridge.

I will let you know if something comes out.

Regards,

Florian B.