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Altera_Forum
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16 years ago

Tristate Bridge between 32-bit and 16-bit data bus

Hello all! I am trying to write some data to an external 16-bit MRAM memory. This MRAM memory has a tristate data bus, so in my SOPC system, the CPU connects to an Avalon-MM Tristate Bridge, th...
Altera_Forum's avatar
Altera_Forum
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16 years ago

After using the RTL viewer of my project, I can see that at the input of my tristate bridge, the slave writedata bus is only 16 bits wide.

Between my 32-bit NIOS cpu and the tristate bridge, the 32-bit data bus to 16-bit data bus conversion is made by a "cpu_data_master_arbitrator", but the "write" request signal is not processed by this arbitrator.

In the same manner, between my custom master component, called "scope_controller", and the tristate, the 32-bit data bus to 16-bit data bus conversion is made by a "scope_controller_m1_arbitrator", which does not process the "write" request signal also.

Therefore, my guess is that the master component connected to the tristate has to handle the write/read features regarding the data bus width of the slave component.

Do you agree with this statement?