Forum Discussion
Altera_Forum
Honored Contributor
16 years agoSorry, I made some mistakes in my first post. Actually, when the CPU performs a 32-bit write request, two 16-bit write requests are performed by the tristate bridge. The issue occurs when a custom component performs a 32-bit write request to the MRAM. In this case, only one 16-bit write request is performed by the tristate bridge.
Do you know why?