Stratix IV and DDR3

Question

Has anyone done a Stratix IV design with DDR3? I've got a little test project set up. The DDR3 controller is instantiated inside SoPC builder. During synthesis the following error is given:  Error: Illegal connection found on I/O input buffer primitive prism_main_sopc:prism_main_sopc_inst|a_ddr3:the_a_ddr3|a_ddr3_controller_phy:a_ddr3_controller_phy_inst|a_ddr3_phy:a_ddr3_phy_inst|a_ddr3_phy_alt_mem_phy:a_ddr3_phy_alt_mem_phy_inst|a_ddr3_phy_alt_mem_phy_clk_reset:clk|gen_mimic_diff_ibuf.fb_clk_ibuf. Source IO prism_main_sopc:prism_main_sopc_inst|a_ddr3:the_a_ddr3|a_ddr3_controller_phy:a_ddr3_controller_phy_inst|a_ddr3_phy:a_ddr3_phy_inst|a_ddr3_phy_alt_mem_phy:a_ddr3_phy_alt_mem_phy_inst|a_ddr3_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT.mem_clk_obuf~0 also drives out to other destination than the buffer.  Following the error down to the source file reveals the following IO buffer instance:          stratixiii_io_ibuf fb_clk_ibuf(
            .i      (mem_clk),
            .ibar   (mem_clk_n),
            .o      (fb_clk)
        );  I believe this is the fedback clock used for the mimic path in the DDR3 controller. The error statement made by Quartus is of course true. mem_clk is driven directly out of the device in addition to feeding this buffer.   It's curious that the instance is that of a Stratix III IO buf rather than Stratix IV. It's not totally absurd that Altera just uses the Stratix III version for both. Regardless, the question remains as to why the error is ocurring.  Perhaps I'm just running into preliminary Stratix IV support issues. Any ideas?  Jake

altera_forum · Answer

Problem solved. The top-level clock output pins need to be declared as bidirectional. I had declared them as outputs.  Jake

altera_forum · Answer

Thanks. I was beating my head against the wall when I finally saw your answer. I appreciate you posting a solution once you discovered the error.   Ziad:)

altera_forum · Answer

Hi,

i have the same problem with my DDR3 HPFII controller.

But your solution doesn't help me. The clock pins from the controller are bidirectional on the toplevel. I check with Quartus II RTL viewer and the pins are bidirectional too. I had an old compalation with these HPF Controller an singla rank sodimm, there was no error. Now an sodimm with dual rank this error is shown. Maybe the memory preset is wrong. The sodimm has 2 chip selects. Each for 1 rank.

I try this:

Total Memory chip selects : 2

Chip selects per DIMM : 2

Chip selects per rank : 2

Is this right?

Regards Josef

altera_forum · Answer

You have a dual rank dimm with 2 chip selects, therefore "Chip selects per rank" = 1

altera_forum · Answer

Hi,

I'm also doing the same thing as you did (my mem_bot_clk and mem_bot_clk_n are already in inout mode) in my top level entity but I still have the

"...also drives out to other destination than the buffer" message.

I also checked out the altera solution which is to convert each std_logic_vector(0 downto 0) into std_logic but it seems useless.

I'm actually using Quartus II 11.0 Full Version with a Stratix IV GX 230 and I'm trying to use the Triple Speed Ethernet.

My design worked fine with a Nios II until I decided to add two SGDMA (RX and TX) and the TSE core. (after that my Nios II seems to be turned off but the design still work with signaltap, I use the Nios II only for the printf() )

And my question is, does anyone know how to solve the DDR3 problem with Quartus II 11.0 ?

Best regards,

Michel

Forum Discussion

Stratix IV and DDR3

6 Replies

Recent Discussions

Cyclone 10 GX IBIS-AMI models

PCIe Enumeration Failure for CXL IP

Can't generate F-Tile Ethernet Hard IP Design Example

Agilex 7 slew rate reconfiguration

Constraints not being picked for DCFIFO